User guide

Chapter 17: Transceiver PHY Reset Controller IP Core 17–4
Transceiver PHY Reset Controller Parameters
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
TX PLL
Enable TX PLL channel reset control On/Off
When On, the Transceiver PHY Reset Controller enables the
control of the TX PLL. When Off, the TX PLL controls are
disabled.
pll_powerdown duration
1–999999999
Specifies the duration of the PLL powerdown period in ns.
The value is rounded up to the nearest clock cycle. The
default value is 1000 ns.
Synchronize reset input for PLL
powerdown
On/Off
When On, the Transceiver PHY Reset Controller synchronizes
the PLL powerdown reset with the Transceiver PHY Reset
Controller input clock. When Off, the PLL powerdown reset is
not synchronized. If you select this option, you must also
enable the Synchronize reset input parameter.
Turning this option On prevents equivalent PLLs from being
merged across Transceiver PHY Reset Controllers.
TX Channel
Enable TX channel reset control On/Off
When On, the Transceiver PHY Reset Controller enables the
control logic and associated status signals for TX reset.
When Off, disables TX reset control and status signals.
Use separate TX reset per channel On/Off
When On, each TX channel has a separate reset. When Off,
the Transceiver PHY Reset Controller uses a shared TX reset
controller for all channels.
TX automatic reset recovery mode
Auto
Manual
Expose Port
Specifies the Transceiver PHY Reset Controller behavior
when the
pll_locked signal is deasserted. The following
modes are available:
■ Auto: The associated tx_digital_reset controller
automatically resets whenever the
pll_locked signal is
deasserted.
■ Manual: The associated tx_digital_reset controller is
not reset when the
pll_locked signal is deasserted,
allowing you to choose corrective action.
■ Expose Port: The tx_manual signal is a top-level signal of
the IP Core.
tx_digitalreset duration
1–999999999
Specifies the time in ns to continue to assert the
tx_digitalreset after the reset input and all other gating
conditions are removed. The value is rounded up to the
nearest clock cycle. The default value is 20 ns.
pll_locked input hysteresis
1–999999999
Specifies the amount of hysteresis in ns to add to the
pll_locked status input to filter spurious unreliable
assertions of the
pll_locked signal. A value of 0 adds no
hysteresis. A higher values filters glitches on the
pll_locked signal.
RX Channel
Enable RX channel reset control On/Off
When On, the Transceiver PHY Reset Controller enables the
control logic and associated status signals for RX reset.
When Off, disables RX reset control and status signals.
Table 17–3. General Options (Part 2 of 3)
Name Range Description