User guide

Chapter 17: Transceiver PHY Reset Controller IP Core 17–6
Interfaces
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 17–4 describes the signals in Figure 17–2 in the order that they are shown in the
figure.
Table 17–4. Top-Level Signals (Part 1 of 2)
Signal Name Direction Description
Input Signals
pll_locked[<p>-1:0] Input
Provides the PLL locked status input for each PLL. When asserted,
indicates that the TX PLL is locked. When deasserted, the PLL is not
locked. There is one signal per PLL.
When an IP core uses multiple PLLS, the
pll_select signals specifies
the PLL to use.
pll_select Input
When you select Use separate TX reset per channel, this bus provides
enough inputs to specify an index for each
pll_locked signal to listen
to for each channel.
When you select a shared TX reset, the
pll_select signal specifies the
pll_locked signal used for all channels.
This signal is synchronous to the Transceiver PHY Reset Controller
input clock.
tx_cal_busy[<n>-1:0] Input
This is the calibration status signal from the Transceiver PHY IP Core.
When asserted, calibration is active. When deasserted, calibration has
completed. This signal gates the TX reset sequence. The width of this
signals depends on the number of TX channels.
rx_cal_busy[<n>-1:0] Input
This is calibration status signal from the Transceiver PHY IP Core. When
asserted, calibration is active. When deasserted, calibration has
completed. This signal gates the RX reset sequence.The width of this
signals depends on the number of RX channels.
rx_is_lockedtodata[<n>-1:0] Input
Provides the
rx_is_lockedtodata status from each RX CDR. When
asserted, indicates that a particular RX CDR is ready to receive input
data. If you do not choose separate controls for the RX channels, these
inputs are
AND ed together internally to provide a single status signal.
tx_manual[<n>-1:0] Input
This optional signal places
tx_digitalreset controller under
automatic or manual control.
When asserted, the associated
tx_digitalreset controller does not
automatically respond to deassertion of the
pll_locked signal.
However, the initial
tx_digitalreset sequence still requires a
one-time rising edge on
pll_locked before proceeding.
When deasserted. The associated
tx_digital_reset controller
automatically begins its reset sequence whenever the selected
pll_locked signal is deasserted.
rx_manual[<n>-1:0] Input
This optional signal places
rx_digitalreset controller under
automatic or manual control.
When asserted, the associated
rx_digitalreset controller does not
automatically respond to deassertion of the
rx_is_lockedtodata
signal. When deasserted. The associated
rx_digital_reset
controller automatically begins its reset sequence whenever the selected
rx_is_lockedtodata signal is deasserted.
clock Input
System clock input to the Transceiver PHY Reset Controller from which
all internal logic is driven.