User guide

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–9
Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Differences Between Custom PHY Parameters for Stratix IV and
Stratix V Devices
Table 19–6 lists the Custom PHY parameters and the corresponding ALTGX
megafunction parameters.
Table 19–6. Comparison of ALTGX Megafunction and Custom PHY Parameters (Part 1 of 2)
ALTGX Parameter Name (Default Value) Custom PHY Parameter Name
General
Not available
Device family
Transceiver protocol
Mode of operation
Enable bonding
What is the number of channels? Number of lanes
Which subprotocol will you be using? (×4, ×8) Not available
What is the channel width? Serialization factor
What is the effective data rate? Data rate
What is the input clock frequency? Input clock frequency
tx/rx_8b_10b_mode Enable 8B/10B encoder/decoder
Not available
Enable manual disparity control
Create optional 8B10B status ports
What is the d
eserializer block width?
Single
Double
Deserializer block width:
(1)
Auto
Single
Double
Additional Options
Not available
Enable TX Bitslip
Create rx_coreclkin port
Create tx_coreclkin port
Create rx_recovered_clk port
Create optional ports
Avalon data interfaces
Force manual reset control
Protocol Settings–Word Aligner Word Aligner
Use manual word alignment mode
Use manual bitslipping mode
Use the built-in ‘synchronization state machine’
Word alignment mode
Enable run length violation checking with a run length o
f Run length
What is the word alignment patternWord alignment pattern
What is the word alignment pattern lengthWord aligner pattern length
Protocol Settings—Rate match/Byte order Rate Match
What is the 20-bit rate match pattern1
(usually used for +ve disparity pattern)
Rate match insertion/deletion +ve disparity pattern