User guide

20–2 Additional InformationAdditional Information
Revision History
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
PHY IP Core for PCI Express (PIPE)
November
2012
1.8
■ Added Gen3 support.
■ Added Arria V GZ support.
■ Added ×2 support.
■ Added discussion of link equalization for Gen3.
■ Added timing diagram showing rate change to Gen3.
■ Revised presentation of signals.
■ Corrected the definition of rx_eidleinfersel[3<n>-1:0] .
■ Moved Analog Options to a separate chapter.
■ Updated section on Logical Lane Assignment Restrictions.
■ Removed the following statement from the definition of pll_powerdown. Asserting
pll_powerdown no longer powers down tx_analogreset . tx_analogreset is a separate
signal.
Custom PHY IP Core
November
2012
1.8
■ Added Cyclone V support.
■ Moved Analog Options to a separate chapter.
■ Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Low Latency PHY IP Core
November
2012
1.8
■ Added Cyclone V support.
■ Moved Analog Options to a separate chapter.
■ Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
■ Added RX bitslip option for the word aligner when the 10G PCS is selected.
Deterministic Latency PHY IP Core
November
2012
1.8
■ Added Cyclone V support.
■ Moved Analog Options to a separate chapter.
Stratix V Transceiver Native PHY
November
2012
1.8
■ Added support for Standard and 10G datapaths.
■ Added QPI interface.
■ Moved Analog Options to a separate chapter.
■ Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Arria V Transceiver Native PHY
November
2012
1.8
■ Added support for Standard datapath.
■ Added support for multiple PLLs.
■ Moved Analog Options to a separate chapter.
■ Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Arria V GZ Transceiver Native PHY
November
2012
1.8
■ Initial release.
Date Version Changes Made