User guide

20–10 Additional InformationAdditional Information
Revision History
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Introduction
November
2011
1.3
■ Revised reset section. The 2 options for reset are now the embedded reset controller or
user-specified reset controller.
■ Updated directory names in simulation testbench.
10GBASE-R PHY Transceiver
November
2011
1.3
■ Added support for Stratix V devices.
■ Added section discussing transceiver reconfiguration in Stratix V devices.
■ Removed rx_oc_busy signal which is included in the reconfiguration bus.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
XAUI Transceiver PHY
November
2011
1.3
■ The pma_tx_pll_is_locked is not available in Stratix V devices.
■ Added base data rate, lane rate, input clock frequency, and PLL type parameters.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
■ Added section on dynamic transceiver reconfiguration in Stratix V devices.
■ Removed Timing Constraints section. These constraints are included in the HDL code.
Interlaken Transceiver PHY
November
2011
1.3
■ Added tx_sync_done signal which indicates that all lanes of TX data are synchronized.
■ tx_coreclk_in is required in this release.
■ Added base data rate, lane rate, input clock frequency, and PLL type parameters.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
PHY IP Core for PCI Express (PIPE)
November
2011
1.3
■ Added pll_powerdown bit (bit[0] of 0x044) for manual reset control. You must assert this
bit for 1
s for Gen2 operation.
■ Added PLL type and base data rate parameters.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
Custom Transceiver PHY
November
2011
1.3
■ Added Arria V and Cyclone V support.
■ Added base data rate, lane rate, input clock frequency, and PLL type parameters.
■ Revised reset options. The 2 options for reset are now the embedded reset controller or a
user-specified reset logic.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
Date Version Changes Made