User guide

Additional InformationAdditional Information 20–13
Revision History
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Interlaken PHY Transceiver
May 2011 1.2
■ Added details about the 0 ready latency for tx_ready .
■ Added PLL support to lane rate parameter description in Interlaken PHY General Options.
■ Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core.
The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Added a reference to PHY IP Design Flow with Interlaken for Stratix V Devices which is a
reference design that implements the Interlaken protocol in a Stratix V device.
■ Changed supported metaframe lengths from 1–8191 to 5–8191.
■ Added pll_locked output port.
■ Added indirect_addr register at 0x080 for use in accessing PCS control and status
registers.
■ Added new Bonded group size parameter.
PHY IP Core for PCI Express PHY (PIPE)
May 2011 1.2
■ Renamed to PHY IP Core for PCI Express.
■ Moved dynamic reconfiguration for the transceiver outside of the PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Removed ×2 support.
Custom PHY Transceiver
May 2011 1.2
■ Added presets for the 2.50 GIGE and 1.25GIGE protocols.
■ Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Removed device support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX.
■ Added the following parameters on the General tab:
■ Transceiver protocol
■ Create rx_recovered_clk port
■ Force manual reset control
■ Added optional rx_rmfifoddatainserted , rx_rmfifodatadelted , rx_rlv , and
rx_recovered_clk
as output signals.
■ Added phy_mgmt_waitrequest to the PHY management interface.
■ Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and
reconfig_to_xcvr , respectively.
■ Corrected address for 8-Gbps RX PCS status register in Table 9–18 on page 9–20.
■ Added special pad requirement for Byte ordering pattern. Refer to Table 9–6 on page 9–8.
■ Clarified behavior of the word alignment mode. Added note explaining how to disable all
word alignment functionality.
Low Latency PHY Transceiver
May 2011 1.2
■ Moved dynamic reconfiguration for the transceiver outside of the Low Latency PHY IP Core.
The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Moved dynamics reconfiguration for the transceiver outside of the Custom PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Renamed the tx_parallel_clk signal tx_clkout .
Date Version Changes Made