User guide
Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–7
Clock and Reset Interfaces
November 2012 Altera CorporationAltera Transceiver PHY IP Core
User Guide
Phy_mgmt_clk_reset
is the system-level reset signal.
Phy_mgmt_clk_reset
is also an
input to the Transceiver PHY Reset Controller IP Core which is a separately
instantiated module not included in the 1G/10GbE and 10GBASE-KR variants. The
Transceiver PHY Reset Controller IP Core resets the TX PLL and RX analog circuits
and the TX and RX digital circuits. When complete, the Reset Controller asserts the
tx_ready
and
rx_ready
signals.
f For more information about the Transceiver PHY Reset Controller IP Core, refer to the
Transceiver PHY Reset Controller IP Core chapter in the Altera Transceiver PHY IP Core
User Guide.
Figure 5–3 provides an overview of the clocking for this core. The wrapper ties off
outputs of the PCS and PMA modules that are not required for the 1G/10Gbe IP Core.
Table 5–7 describes the clock and reset signals.
Figure 5–3. Clocks for Standard and 10G PCS and TX PLLs
xgmii_rx_clk
156.25 MHz
xgmii_tx_clk
156.25 MHz
Native PHY
Stratix V STD
RX PCS
Stratix V
TX PMA
tx_coreclkin_1g
125 MHz
Stratix V
RX PMA
TX PLL
TX PLL
40
rx_pld_clk rx_pma_clk
TX serial data
8
GMII TX Data
72
XGMII TX Data & Cntl
RX data
40
TX data
40
TX data
serial data
pll_ref_clk_10g
644.53125 MHz
or
322.265625 MHz
pll_ref_clk_1g
125 MHz
or
62.5 MHz
Stratix V STD
TX PCS
tx_pld_clk tx_pma_clk
8
GMII RX Data
pll_ref_clk_10g
72
XGMII RX Data & Cntl
recovered clk
257.8125 MHz
rx_coreclkin_1g
125 MHz
Stratix V 10G
RX PCS
rx_pld_clk rx_pma_clk
Stratix V 10G
TX PCS
tx_pld_clk tx_pma_clk
fractional
PLL
(instantiate
separately)
GIGE
PCS
GIGE
PCS
Table 5–7. Clock and Reset Signals (Part 1 of 2)
Signal Name Direction Description
rx_recovered_clk
Output
The RX clock which is recovered from the received data. You can use this clock
as a reference to lock an external clock source. Its frequency is 125 or
156.25 MHz.
tx_clkout_1g
Output
GMII TX clock for the 1G TX parallel data source interface. The frequency is
125 MHz.
tx_clkout_10g
Output
XGMII TX clock for the 10GbTX parallel data source interface. The frequency is
257.8125 MHz.