Altera Transceiver PHY IP Core User Guide Subscribe Send Feedback UG-01080 2015.01.12 101 Innovation Drive San Jose, CA 95134 www.altera.
TOC-2 Altera Transceiver PHY IP Core User Guide Contents Introduction to the Protocol-Specific and Native Transceiver PHYs............... 1-1 Protocol-Specific Transceiver PHYs......................................................................................................... 1-1 Native Transceiver PHYs ...........................................................................................................................1-2 Non-Protocol-Specific Transceiver PHYs...................................
Altera Transceiver PHY IP Core User Guide TOC-3 Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option.............................................................................................................. 4-1 10GBASE-KR PHY Release Information................................................................................................. 4-3 Device Family Support.......................................................................................................................
TOC-4 Altera Transceiver PHY IP Core User Guide 1G/10GbE Control and Status Interfaces............................................................................................... 5-12 Register Interface Signals.......................................................................................................................... 5-14 1G/10GbE PHY Register Definitions .....................................................................................................5-15 PMA Registers................
Altera Transceiver PHY IP Core User Guide TOC-5 Interlaken PHY IP Core...................................................................................... 7-1 Interlaken PHY Device Family Support................................................................................................... 7-2 Parameterizing the Interlaken PHY.......................................................................................................... 7-3 Interlaken PHY General Parameters................................
TOC-6 Altera Transceiver PHY IP Core User Guide Parameterizing the Custom PHY.............................................................................................................. 9-3 General Options Parameters.......................................................................................................... 9-3 Word Alignment Parameters......................................................................................................... 9-7 Rate Match FIFO Parameters....................
Altera Transceiver PHY IP Core User Guide TOC-7 Interfaces for Deterministic Latency PHY........................................................................................... 11-15 Data Interfaces for Deterministic Latency PHY..................................................................................11-16 Clock Interface for Deterministic Latency PHY.................................................................................
TOC-8 Altera Transceiver PHY IP Core User Guide Bit Reversal and Polarity Inversion........................................................................................... 13-20 Interfaces...................................................................................................................................................13-23 Common Interface Ports............................................................................................................ 13-23 Standard PCS Interface Ports.
Altera Transceiver PHY IP Core User Guide TOC-9 Simulation Support..................................................................................................................................15-34 Transceiver Reconfiguration Controller IP Core Overview............................ 16-1 Transceiver Reconfiguration Controller System Overview................................................................. 16-2 Transceiver Reconfiguration Controller Performance and Resource Utilization.................
TOC-10 Altera Transceiver PHY IP Core User Guide Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration......... 16-46 Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration ....16-47 Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration......................................................................................................................
Altera Transceiver PHY IP Core User Guide TOC-11 Migrating from Stratix IV to Stratix V Devices Overview............................... 20-1 Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers....................... 20-2 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices......................... 20-3 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices.....................................
1 Introduction to the Protocol-Specific and Native Transceiver PHYs 2015.01.19 UG-01080 Subscribe Send Feedback The Arria V, Cyclone V, and Stratix V support three types of transceiver PHY implementations or customization. The three types of transceiver PHY implementations are the following: • Protocol-specific PHY • Non-protocol-specific PHY • Native transceiver PHY The protocol-specific transceiver PHYs configure the PMA and PCS to implement a specific protocol.
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1-4 UG-01080 2015.01.19 Non-Protocol-Specific Transceiver PHYs Datapaths Standard: Stratix V Arria V Arria V GZ Cyclone V Yes Yes Yes Yes Yes - Yes - This datapath provides a complete PCS and PMA for the TX and RX channels. You can customize the Standard datapath by enabling or disabling individual modules and specifying data widths. 10G: This is a high performance datapath. It provides a complete PCS and PMA for the TX and RX channels.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller 1-5 PCS The PCS implements part of the physical layer specification for networking protocols. Depending upon the protocol that you choose, the PCS may include many different functions. Some of the most commonly included functions are: 8B/10B, 64B/66B, or 64B/67B encoding and decoding, rate matching and clock compensation, scrambling and descrambling, word alignment, phase compensation, error monitoring, and gearbox.
1-6 UG-01080 2015.01.19 Running a Simulation Testbench The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the transceiver to enable successful operation. Because the Transceiver PHY Reset Controller IP is available in clear text, you can also modify it to meet your requirements. For more information about the Transceiver PHY Reset Controller, refer to Transceiver Reconfiguration Controller IP Core.
UG-01080 2015.01.19 Running a Simulation Testbench 1-7 Figure 1-3: Directory Structure for Generated Files . v or .vhd - the parameterized transceiver PHY IP core .qip - lists all files used in the transceiver PHY IP design .
1-8 UG-01080 2015.01.19 Running a Simulation Testbench File Name Description sv_xcvr_native.sv Defines the transceiver. It includes instantiations of the PCS and PMA modules and Avalon-MM PHY management interface. stratixv_hssi_ _rbc. sv These files perform rule based checking for the module specified. For example, if the PLL type, data rate, and FPGA fabric transceiver interface width are not compatible, the checker reports an error. altera_wait_generate.
UG-01080 2015.01.19 Unsupported Features 1-9 When you specify multiple .spd files, the ip-make-simscript utility generates a single simulation script containing all required simulation information. The default value of TOP_LEVEL_NAME is the TOP_LEVEL_NAME defined in the IP core or Qsys .spd file. If this is not the top-level instance in your design, specify the top-level instance of your testbench or design.
2 Getting Started Overview 2015.01.19 UG-01080 Subscribe Send Feedback This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications.
2-2 UG-01080 2015.01.19 Design Flows Related Information • Altera • Altera Licensing • Altera Software Installation and Licensing Design Flows This section describes how to parameterize Altera IP cores.
UG-01080 2015.01.19 MegaWizard Plug-In Manager Flow 2-3 MegaWizard Plug-In Manager Flow This section describes how to specify parameters and simulate your IP core with the MegaWizard Plug-In Manager. The MegaWizard™ Plug-In Manager flow allows you to customize your IP core and manually integrate the function into your design. Specifying Parameters To specify IP core parameters, follow these steps: 1. 2. 3. 4. Create a Quartus II project using the New Project Wizard available from the File menu.
2-4 Simulate the IP Core UG-01080 2015.01.19 Note: The Finish button may be unavailable until all parameterization errors listed in the messages window are corrected. 8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. You can now integrate your custom IP core instance in your design, simulate, and compile.
3 10GBASE-R PHY IP Core 2015.01.19 UG-01080 Subscribe Send Feedback The Altera 10GBASE-R PHY IP Core implements the functionality described in IEEE Standard 802.3 Clause 45. It delivers serialized data to an optical module that drives optical fiber at a line rate of 10.3125 gigabits per second (Gbps). In a multi-channel implementation of 10GBASE-R, each channel of the 10GBASE-R PHY IP Core operates independently.
3-2 UG-01080 2015.01.19 10GBASE-R PHY IP Core To make the most effective use of this soft PCS and PMA configuration for Stratix IV GT devices, you can group up to four channels in a single quad and control their functionality using one Avalon-MM PHY management bridge, transceiver reconfiguration module, and low controller.
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3-6 UG-01080 2015.01.19 10GBASE-R PHY Release Information Table 3-2: Latency for TX and RX PCS and PMA Stratix V Devices PCS (Parallel Clock Cycles) 32-bit PMA Width Minimum 40-bit PMA Width Maximum Minimum PMA (UI) Maximum TX 7 12 8 12 124 RX 14 33 15 34 43 Related Information • IEEE 802.3 Clause 49 • 10-Gbps Ethernet MAC MegaCore Function User Guide • Transceiver Configurations in Stratix V Devices 10GBASE-R PHY Release Information Release information for the IP core.
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UG-01080 2015.01.19 General Option Parameters 3-9 General Option Parameters This section describes general parameters. This section describes the 10GBASE-R PHY parameters, which you can set using the MegaWizard PlugIn Manager. Table 3-8: General Options Name Value Description General Options Device family Arria V Specifies the target device. Arria V GZ Stratix IV GT Stratix V Number of channels 1-32 Mode of operation Duplex TX Only The total number of 10GBASE-R PHY channels.
3-10 UG-01080 2015.01.19 General Option Parameters Name PCS / PMA interface width Value Description 32 For Stratix V and Arria V GZ devices only: 40 Specifies the data interface width between the 10G PCS and the transceiver PMA. Smaller width corresponds to lower PCS latency but higher frequency. • For 40 bit width, rx_recovered_clock is 257.8125 MHz and the gearbox ratio is 66:40. • For 40 bit width, rx_recovered_clock is 322.265626 MHz and the gearbox ratio is 66:32.
UG-01080 2015.01.19 General Option Parameters Name Value 3-11 Description Enable embedded reset control On/Off When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogreset , rx_analogreset, tx_digitalreset, rx_ digitalreset, and pll_powerdown which are top-level ports of the Custom Transceiver PHY. You may also use the Transceiver PHY Reset Controller to reset the transceivers.
3-12 UG-01080 2015.01.19 Analog Parameters for Stratix IV Devices pma_bonding_master to the 10GBASE-R instance name. You must substitute the instance name from your design for the instance name shown in quotation marks.
UG-01080 2015.01.19 10GBASE-R PHY Interfaces Name Receiver common mode voltage Value Tri-State 3-13 Description Specifies the RX common mode voltage. 0.82V 1.1v Receiver termination resistance OCT_85_OHMS OCT_100_OHMs Indicates the value of the termination resistor for the receiver.
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UG-01080 2015.01.19 10GBASE-R PHY Data Interfaces Signal Name xgmii_tx_dc_[71:0] Direction Input 3-15 Description Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control.
3-16 UG-01080 2015.01.19 10GBASE-R PHY Data Interfaces Signal Name Direction Description rx_data_ready [-1:0] Output When asserted, indicates that the PCS is sending data to the MAC. Because the readyLatency on this Avalon-ST interface is 0, the MAC must be ready to receive data whenever this signal is asserted. After rx_ ready is asserted indicating the exit from the reset state, the MAC should store xgmii_rx_ dc_[71:0] in each cycle where rx_data_ ready is asserted.
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3-18 UG-01080 2015.01.19 Optional Reset Control and Status Interface Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs Signal Name Direction Description rx_block_lock Output Asserted to indicate that the block synchron‐ izer has established synchronization. rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4. rx_recovered_clk[:0] Output This is the RX clock, which is recovered from the received data stream.
UG-01080 2015.01.19 10GBASE-R PHY Clocks for Arria V GT Devices Signal Name Direction 3-19 Description tx_digitalreset[-1:0] Input When asserted, reset all blocks in the TX PCS. If your design includes bonded TX PCS channels, refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design. tx_analogreset[-1:0] Input When asserted, resets all blocks in the TX PMA.
3-20 UG-01080 2015.01.19 10GBASE-R PHY Clocks for Arria V GZ Devices Figure 3-7: Arria V GT Clock Generation and Distribution 10GBASE-R Transceiver Channel - Arria V GT TX 64 64 TX PCS (soft) TX PMA (hard) 161.1328 MHz xgmii_tx_clk 156.25 MHz 80 10.3125 Gbps pll_ref_clk 644.53125 MHz TX PLL RX 64 RX PCS (soft) rx_coreclkin 64 161.1328 MHz RX PMA (hard) 80 10.
UG-01080 2015.01.19 10GBASE-R PHY Clocks for Stratix IV Devices 3-21 Figure 3-8: Arria V GZ Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Arria V GZ TX 40 64-bit data, 8-bit control xgmii_tx_clk TX PCS TX PMA 257.8125 MHz RX RX PCS 156.25 MHz rx_coreclkin pll_ref_clk 644.53125 MHz 10.3125 Gbps serial 40 64-bit data, 8-bit control xgmii_rx_clk TX PLL 10.3125 Gbps serial RX PMA 257.
3-22 UG-01080 2015.01.19 10GBASE-R PHY Clocks for Stratix V Devices Figure 3-9: Stratix IV Clock Generation and Distribution 10GBASE-R Transceiver Channel - Stratix IV GT TX 40 64-bit data, 8-bit control xgmii_tx_clk TX PCS (soft IP) 20 TX PCS (hard IP) 257.8125 MHz /2 TX PMA 516.625 MHz TX PLL 10.3125 Gbps serial pll_ref_clk 644.53125 MHz 5/4 RX 40 64-bit data, 8-bit control xgmii_rx_clk RX PCS (soft IP) RX PCS (hard IP) 257.8125 MHz 156.25 MHz 10.
UG-01080 2015.01.19 10GBASE-R PHY Register Interface and Register Descriptions 3-23 Figure 3-10: Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix V TX 40 64-bit data, 8-bit control xgmii_tx_clk TX PCS TX PMA 257.8125 MHz RX RX PCS 156.25 MHz rx_coreclkin pll_ref_clk 644.53125 MHz 10.3125 Gbps serial 40 64-bit data, 8-bit control xgmii_rx_clk TX PLL 10.3125 Gbps serial RX PMA 257.
3-24 UG-01080 2015.01.19 10GBASE-R PHY Register Interface and Register Descriptions Table 3-15: Avalon-MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input The clock signal that controls the Avalon-MM PHY management, interface. For Stratix IV devices, the frequency range is 37.5-50 MHz.
UG-01080 2015.01.19 10GBASE-R PHY Register Interface and Register Descriptions Word Addr Bit R/W Name 0x021 [31:0] RW cal_blk_powerdown 0x022 [31:0] RO pma_tx_pll_is_locked 3-25 Description Writing a 1 to channel powers down the calibration block for channel . This register is only available if you select Use external PMA control and reconfig on the Additional Options tab of the GUI. Bit[P] indicates that the TX clock multiplier unit CMU PLL [P] is locked to the input reference clock.
3-26 UG-01080 2015.01.19 10GBASE-R PHY Register Interface and Register Descriptions Word Addr Bit [31:0] R/W RW Name reset_fine_control Description You can use the reset_fine_ register to create your own reset sequence. The reset control module performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4,0] are reserved.
UG-01080 2015.01.19 10GBASE-R PHY Register Interface and Register Descriptions Word Addr 0x067 Bit [31:0] R/W RO Name pma_rx_is_lockedtoref 3-27 Description When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit corresponds to channel .
3-28 UG-01080 2015.01.19 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices Word Addr Bit R/W Name [5:0] R BER_COUNT[5:0] [13:6] R ERROR_BLOCK_COUNT[7:0] [14] R LATCHED_HI_BER [15] R LATCHED_BLOCK_LOCK 0x083 Description For Stratix IV devices only, records the bit error rate (BER). From block: BER monitor For Stratix IV devices only, records the number of blocks that contain errors. From Block: Block synchron‐ izer Latched version of HI_BER .
UG-01080 2015.01.19 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices Signal Name Direction Output reconfig_from_xcvr [(/4) 17-1:0] 3-29 Description Reconfiguration RAM. The PHY device drives this RAM data to the transceiver reconfiguration IP. This signal is only available in Stratix IV devices.
3-30 UG-01080 2015.01.19 1588 Delay Requirements 1588 Delay Requirements The 1588 protocol requires symmetric delays or known asymmetric delays for all external connections. In calculating the delays for all external connections, you must consider the delay contributions of the following elements: • • • • The PCB traces The backplane traces The delay through connectors The delay through cables Accurate calculation of the channel-to-channel delay is important in ensuring the overall system accuracy.
UG-01080 2015.01.19 10GBASE-R PHY TimeQuest Timing Constraints 3-31 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct| receive_pcs*|clkout}] -to pll_ref_clk -setup 0.1 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_direct| auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -setup 0.08 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct| receive_pcs*|clkout}] -to pll_ref_clk -hold 0.
3-32 10GBASE-R PHY Simulation Files and Example Testbench UG-01080 2015.01.19 Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V Native PHY for details. Related Information • SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths.
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option 4 2015.01.19 UG-01080 Subscribe Send Feedback The Backplane Ethernet 10GBASE-KR PHY MegaCore® function is available for Stratix® V and Arria V GZ devices. This transceiver PHY allows you to instantiate both the hard Standard PCS and the higher performance hard 10G PCS and hard PMA for a single Backplane Ethernet channel. It implements the functionality described in the IEEE Std 802.3ap-2007 Standard.
4-2 UG-01080 2015.01.19 Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Figure 4-1: 10GBASE-KR PHY MegaCore Function and Supporting Blocks Altera Device with 10.3125+ Gbps Serial Transceivers 10GBASE-KR PHY MegaCore Function Native PHY Hard IP TX XGMII Data @156.
UG-01080 2015.01.19 10GBASE-KR PHY Release Information 4-3 10GBASE-KR PHY Release Information Table 4-1: 10GBASE-KR PHY Release Information Item Description Version 13.1 Release Date November 2013 Ordering Codes IP-10GBASEKR PHY (primary) Product ID 0106 Vendor ID 6AF7 Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
4-4 UG-01080 2015.01.19 Parameterizing the 10GBASE-KR PHY The following table shows the typical expected resource utilization for selected configurations using the current version of the Quartus II software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v14.
UG-01080 2015.01.19 10GBASE-KR Link Training Parameters 4-5 Related Information • • • • • • 10GBASE-KR Link Training Parameters on page 4-5 10GBASE-KR Auto-Negotiation and Link Training Parameters on page 4-7 10GBASE-R Parameters on page 4-7 1GbE Parameters on page 4-9 Speed Detection Parameters on page 4-10 PHY Analog Parameters on page 4-10 10GBASE-KR Link Training Parameters The 10GBASE-KR variant provides parameters to customize the Link Training parameters.
4-6 UG-01080 2015.01.19 10GBASE-KR Link Training Parameters Name Value VMINRULE 0-63 VODMINRULE 0-63 VPOSTRULE 0-31 VPRERULE 0-15 PREMAINVAL 0-63 PREPOSTVAL 0-31 PREPREVAL 0-15 INITMAINVAL 0-63 INITPOSTVAL 0-31 INITPREVAL 0-15 Altera Corporation Description Specifies the minimum VOD. The default value is 9 which represents 165 mV. Specifies the minimum VOD for the first tap. The default value is 22 which represents 440mV.
UG-01080 2015.01.19 10GBASE-KR Auto-Negotiation and Link Training Parameters 4-7 10GBASE-KR Auto-Negotiation and Link Training Parameters Table 4-5: Auto Negotiation and Link Training Settings Name AN_PAUSE Pause Ability Range 0-8 Description Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word. C2 = reserved. C1 is the same as ASM_DIR. C0 is the same as PAUSE. CAPABLE_FEC ENABLE_FEC (request) 0-3 Depends upon FEC. Local device FEC abiity F1:0 = D47:46. F0 is Capability.
4-8 UG-01080 2015.01.19 10GBASE-R Parameters Parameter Name Reference clock frequency Options 644.53125MHz 322.265625MHz PLL Type ATX Description Specifies the input reference clock frequency. The default is 322.265625MHz. Specifies the PLL type. You can specify either a CMU or ATX PLL. The ATX PLL has better jitter performance at higher data rates than the CMU PLL. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.
UG-01080 2015.01.19 1GbE Parameters Parameter Name Enable FEC status ports Options On/Off 4-9 Description When you turn this option the core includes the rx_block_lock, rx_parity_good, rx_parity_ invalid, and tx_frame signals. Note: This parameter is not implemented in the early access release. Related Information Analog Parameters Set Using QSF Assignments on page 19-1 1GbE Parameters The 1GbE parameters allow you to specify options for the 1GbE mode.
4-10 UG-01080 2015.01.19 Speed Detection Parameters Speed Detection Parameters Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/ 10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GE and 10GE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
UG-01080 2015.01.19 4-11 10GBASE-KR PHY IP Core Functional Description In this figure, the colors have the following meanings: • Green-Altera- Cores available Quartus II IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller. • Orange-Arbitration Logic Requirements. Logic you must design, including the Arbiter and State Machine.
4-12 UG-01080 2015.01.19 10GBASE-KR PHY IP Core Functional Description • An embedded processor mode to override the state-machine-based training algorithm. This mode allows an embedded processor to establish link data rates instead of establishing the link using the state-machine-based training algorithm. The following figure illustrates the link training process, where the link partners exchange equalization data.
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4-14 UG-01080 2015.01.19 10GBASE-KR PHY Arbitration Logic Requirements Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto negotiation module is reset. The following figures illustrate the handshaking between the Auto Negotiation, Link Training, Sequencer and Transceiver Reconfiguration Controller blocks. Reconfig controller should use lt_start_rc signal in combination with main_rc, post_rc, pre_rc, and tap_to_upd to change TX equalization settings.
UG-01080 2015.01.19 10GBASE-KR PHY State Machine Logic Requirements 4-15 • Channel number—specifies the requested channel • Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel 2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received. 3. Pass the selected channel and rate information or PMA reconfiguration information for LT to the state machine for processing. 4.
4-16 UG-01080 2015.01.19 Forward Error Correction (Clause 74) Figure 4-7: FEC Functional Block Diagram XGMII PCS Transmit PCS Clause 49 Scramble Gearbox FEC Clause 74 FEC (2112,2080) Encoder PMA Service Interface PMA Clause 51 PCS Receive Encode Decode Descramble BER and Sync Header Monitor Block Sync FEC (2112,2080) Decoder and Block Sync XSBI PMA Sublayer MDI The FEC capability is encoded in the FEC Ability and FEC Requested bits of the base Link Codeword.
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4-18 Forward Error Correction (Clause 74) UG-01080 2015.01.19 • FEC Block Synchronizer: The FEC block synchronizer achieves FEC block delineation by locking to correctly received FEC blocks. An algorithm with hysteresis maintains block and word delineation. • FEC Descrambler: The FEC descrambler descrambles the received data to regenerate unscrambled data utilizing the original FEC scrambler polynomial.
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4-20 UG-01080 2015.01.19 10GBASE-KR PHY Clock and Reset Interfaces Related Information Component Interface Tcl Reference 10GBASE-KR PHY Clock and Reset Interfaces This topic provides a block diagram of the 10GBASE-KR clock and reset connectivity and describes the clock and reset signals. Use the Transceiver PHY Reset Controller IP Core to automatically control the transceiver reset sequence.
UG-01080 2015.01.19 10GBASE-KR PHY Clock and Reset Interfaces 4-21 Table 4-10: Clock and Reset Signals Signal Name Direction Description rx_recovered_clk Output The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 257.8125 MHz. tx_clkout_1g Output GMII TX clock for the 1G TX parallel data source interface. The frequency is 125 MHz.
4-22 UG-01080 2015.01.19 10GBASE-KR PHY Data Interfaces • Transceiver Reconfiguration Controller IP Core Overview on page 16-1 10GBASE-KR PHY Data Interfaces The following table describes the signals in the XGMII and GMII interfaces. The MAC drives the TX XGMII and GMII signals to the 10GBASE-KR PHY. The 10GBASE-KR PHY drives the RX XGMII or GMII signals to the MAC.
UG-01080 2015.01.19 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data 4-23 10GBASE-KR GMII Data Interface gmii_rx_err Output When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame. gmii_rx_dv Output When asserted, indicates the start of a new frame. It remains asserted until the last byte of data on the frame is present on gmii_rx_d . led_char_err Output 10-bit character error.
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UG-01080 2015.01.19 10GBASE-KR PHY Control and Status Interfaces 4-25 10GBASE-KR PHY Control and Status Interfaces The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY. Table 4-14: Control and Status Signals Signal Name Direction Description rx_block_lock Output Asserted to indicate that the block synchronizer has established synchronization. rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4.
4-26 UG-01080 2015.01.19 10GBASE-KR PHY Control and Status Interfaces Signal Name Direction Description ref_clk_1g input. The random error without a rate match FIFO mode is: • +/- 1 ns at 1000 Mbps • +/- 5 ns at 100 Mbps • +/- 25 ns at 10 Mbps rx_sync_status Output When asserted, indicates the Standard PCS word aligner has aligned to in incoming word alignment pattern. tx_pcfifo_error_1g Output When asserted, indicates that the Standard PCS TX phase compensation FIFO is full.
UG-01080 2015.01.19 Daisy-Chain Interface Signals Signal Name Direction 4-27 Description rx_latency_adj_10g[15:0] Output When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles. tx_latency_adj_10g[15:0] Output When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.
4-28 UG-01080 2015.01.19 Embedded Processor Interface Signals Table 4-15: Daisy Chain Interface Signals Signal Name Direction Description dmi_mode_en Input When asserted, enable Daisy Chain mode. dmi_frame_lock Input When asserted, the daisy chain state machine has locked to the training frames. dmi_rmt_rx_ready Input Corresponds to bit 15 of Status report field. When asserted, the remote receiver. dmi_lcl_coefl[5:0] Input Local update low bits[5:0].
UG-01080 2015.01.19 Dynamic Reconfiguration Interface Signals 4-29 Table 4-16: Embedded Processor Interface Signals Signal Name Direction Description upi_mode_en Input When asserted, enables embedded processor mode. upi_adj[1:0] Input Selects the active tap. The following encodings are defined: • 2'b01: Main tap • 2'b10: Post-tap • 2'b11: Pre-tap upi_inc Input When asserted, sends the increment command. upi_dec Input When asserted, sends the decrement command.
4-30 UG-01080 2015.01.19 Dynamic Reconfiguration Interface Signals Signal Name Direction Description Output Reconfiguration signals to the Reconfiguration Design Example. grows linearly with the number of reconfiguration interfaces. rc_busy Input When asserted, indicates that reconfiguration is in progress. lt_start_rc Output When asserted, starts the TX PMA equalization reconfiguration. main_rc[5:0] Output The main TX equalization tap value which is the same as VOD.
UG-01080 2015.01.19 Dynamic Reconfiguration Interface Signals Signal Name pcs_mode_rc[5:0] Direction Output 4-31 Description Specifies the PCS mode for reconfig using 1-hot encoding. The following modes are defined: • • • • • • 6'b000001: Auto-Negotiation mode 6'b000010: Link Training mode 6'b000100: 10GBASE-KR data mode 6'b001000: GigE data mode 6'b010000: Reserved 6'b100000:10G data mode with FEC dfe_start_rc Output When asserted, starts the RX DFE equalization of the PMA.
4-32 UG-01080 2015.01.19 Register Interface Signals Signal Name Direction Input rxeq_done Description Link training requires RX equalization to be complete. Tie this signal to 1 to indicate that RX equalization is complete. Register Interface Signals The Avalon-MM master interface signals provide access to all registers.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions 4-33 Notes: • Unless otherwise indicated, the default value of all registers is 0. • Writing to reserved or undefined register addresses may have undefined side effects. • To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to change the register values.
4-34 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 18 RW 0 R SEQ Link Ready 1 R SEQ AN timeout 2 R SEQ LT timeout When set, indicates that the Sequencer has had a timeout. 13:8 R SEQ Reconfig Mode[5:0] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined: Assert KR FEC Request When set to 1, indicates that the core is requesting the FEC ability.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 0xB4 31:0 RSC Name FEC Uncorrected Blocks 0 RW 1 RW 2 RW 3 R 4 RW 5 RW Override AN 0 RW Reset AN 4 RW Restart AN TX SM 8 RW AN Next Page 1 RO AN page received 2 RO AN Complete 0xC0 AN enable AN base pages ctrl AN next pages ctrl Local device remote fault Force TX nonce value 0xC1 0xC2 Description Counts the number of uncorrectable FEC blocks. Resets to 0 when read.
4-36 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 3 RO 4 RO AN RX SM Idle 5 RO AN Ability 6 RO AN Status 7 RO LP AN Ability 8 RO Enable FEC 9 RO Seq AN Failure 17:12 RO AN ADV Remote Fault KR AN Link Ready[5:0] Description When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 4-37 Description • • • • • • [4:0]: Selector [9:5]: Echoed nonce which are set by the state machine [12:10]: Pause bits [13]: Remote Fault bit [14]: ACK which is controlled by the SM [15]: Next page bit Bit 49, the PRBS bit, is generated by the Auto-Negotiation TX state machine. 21:16 RW Override AN_ TECH[5:0] Specifies an AN_TECH value to override.
4-38 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit 0xC5 15:0 R/W RW Name User Next page low Description The Auto-Negotiation TX state machine uses these bits if the Auto-Negotiation next pages ctrl bit is set. The following bits are defined: • • • • • [11]: Toggle bit [12]: ACK2 bit [13]: Message Page (MP) bit [14]: ACK controlled by the state machine [15]: Next page bit For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit 24:0 R/W RO Name AN LP ADV Tech_ A[24:0] 4-39 Description Received technology ability field bits of Clause 73 Auto-Negotiation. The 10GBASE-KR PHY supports A0 and A2. The following protocols are defined: • • • • • • • A0 1000BASE-KX A1 10GBASE-KX4 A2 10GBASE-KR A3 40GBASE-KR4 A4 40GBASE-CR4 A5 100GBASE-CR10 A24:6 are reserved For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.
4-40 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 7:4 RW 11:8 RW 14:12 RW Name main_step_cnt [3:0] prpo_step_cnt [3:0] equal_cnt [2:0] Description Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0010. Specifies the number of equalization steps for each pre- and post- tap update. From 16-31 steps are possible.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 22:20 RW Name rx_ctle_mode 4-41 Description RX CTLE mode in the Link Training algorithm. The default value is 3'b000. The following encodings are defined: • 3'b000: CTLE tuning in link training is disabled. Retains user set value of CTLE. • 3'b001: Reserved. • 3'b010: Reserved. • 3'b011: CTLE tuning in link training is enabled. • 3'b100 to 3'b111: reserved.
4-42 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr 0xD2 0xD3 Bit R/W Name 0 RO 1 RO 2 RO 3 RO 4 RO 5 RO 6 RO 7 RO CTLE Tuning Error 9:0 RW ber_time_frames Link Trained Receiver status Link Training Frame lock Link Training Start-up protocol status Link Training failure Link Training Error Link Training Frame lock Error CTLE Frame Lock Loss Description When set to 1, the receiver is trained and is ready to receive data.
UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 19:10 RW Name ber_time_k_frames 4-43 Description Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/ bits to match the following values: • A value of 3 is about 10 7 bits = about 1.
4-44 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit 13:8 R/W RO Name LD coefficient status[5:0] Description Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel.
UG-01080 2015.01.19 Word Addr 10GBASE-KR PHY Register Definitions Bit 23 R/W RO or RW 29:24 RO Name LP Preset Coefficients LP coefficient status[5:0] 4-45 Description When set to 1, The local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit is defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.
4-46 UG-01080 2015.01.19 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 5:0 R 12:8 R 19:16 R 0xD5 Name LT VOD setting LT Post-tap setting LT Pre-tap setting 23:20 R RXEQ CTLE Setting 25:24 R RXEQ CTLE Mode 27:26 R RXEQ DFE Mode 5:0 LT VODMAX ovrd RW Description Stores the most recent VOD setting that LT specified using the Transceiver Reconfiguration Controller IP core. It reflects Link Partner commands to fine-tune the VOD.
UG-01080 2015.01.19 PMA Registers Word Addr Bit R/W 20:16 RW Name 4-47 Description LT VPOST ovrd Override value for the VPOSTRULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel. The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.
4-48 UG-01080 2015.01.19 PCS Registers Addr Bit Access 0x64 [31:0] RW 0x65 [31:0] RW 0x66 [31:0] RO 0x67 [31:0] RO Name Description pma_rx_set_ locktodata When set, programs the RX CDR PLL to lock to the incoming data. pma_rx_set_ locktoref When set, programs the RX clock data recovery (CDR) PLL to lock to the reference clock. pma_rx_is_ lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode.
UG-01080 2015.01.19 Creating a 10GBASE-KR Design 4-49 Table 4-22: PCS Registers Addr Bit 0x80 31:0 Acce ss Name Description RW Indirect_addr 2 RW RCLR_ERRBLK_CNT 3 RW RCLR_BER_COUNT 1 RO HI_BER 2 RO BLOCK_LOCK 0x82 3 RO TX_FULL When set to 1, the TX_FIFO is full. 4 RO RX_FULL When set to 1, the RX_FIFO is full. 5 RO RX_SYNC_HEAD_ERROR When set to 1, indicates an RX synchronization error. 6 RO RX_SCRAMBLER_ERROR When set to 1, indicates an RX scrambler error.
4-50 UG-01080 2015.01.19 Editing a 10GBASE-KR MIF File 7. Create a MIF for each configuration and associate each MIF with a ROM created in Step 6. For example, create a MIF for 1G with 1588 , a MIF for 10G with 1588, and a MIF for AN/LT. AN/LT MIF is is used to reconfigure the PHY into low latency mode during AN/LT. These MIFs are the three configurations used in the MIF streaming process. The example design contains five required MIFs (1G, 10G, 1G with 1588,10G with 1588 and AN/LT).
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4-52 UG-01080 2015.01.19 Design Example Design Example Figure 4-12: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G) Ethernet Channels NF_DE_WRAPPER Test Harness Management Master ISSP Clock and Reset XGMII Test Harness Source XGMII Source JTAG-toAvalon-MM Master TH0_ADDR = 0xF nnn XGMII Sink XGMII Sink XGMII GEN XGMII GEN XGMII CHK XGMII CHK TH1_ADDR ... = 0xE nnn ...
UG-01080 2015.01.19 SDC Timing Constraints 4-53 SDC Timing Constraints The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V Native PHY for details. Related Information SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths.
1G/10 Gbps Ethernet PHY IP Core 5 2015.01.19 UG-01080 Subscribe Send Feedback The 1G/10 Gbps Ethernet PHY MegaCore® (1G/10GbE) function allows you to instantiate both the Standard PCS and the higher performance 10G PCS and a PMA. The Standard PCS implements the 1 GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard standard.
5-2 UG-01080 2015.01.19 1G/10GbE PHY Release Information Figure 5-1: Level Modules of the 1G/10GbE PHY MegaCore Function Altera Device with 10.3125+ Gbps Serial Transceivers 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257.8 MHz TX XGMII Data @156.
UG-01080 2015.01.19 Device Family Support Item 5-3 Description Product ID 0106 Vendor ID 6AF7 Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device.
5-4 UG-01080 2015.01.19 Parameterizing the 1G/10GbE PHY PHY Module Options 1GbE/10GbE - 1GbE only with Sequencer ALMs 400 M20K Memory Logic Registers 0 700 1GbE/10GbE - 1GbE/10GbE 1000 with 1588 4 2000 1GbE/10GbE - 1GbE/10GbE 1100 with 1588 and Sequencer 4 2000 Parameterizing the 1G/10GbE PHY The 1G/10GbE PHY IP Core is available for the Arria V GZ and Stratix V device families. The IP variant allows you specify either the Backplane-KR or 1Gb/10Gb Ethernet variant.
UG-01080 2015.01.19 Speed Detection Parameters Parameter Name Options 5-5 Description Enable IEEE 1588 Precision Time On/Off Protocol When you turn this option On, the core includes a module in the PCS to implement the IEEE 1588 Precision Time Protocol. PHY ID (32 bit) An optional 32-bit value that serves as a unique identifier for a particular type of PCS.
5-6 UG-01080 2015.01.19 PHY Analog Parameters Parameter Name Link fail inhibit time for 10Gb Ethernet Link fail inhibit time for 1Gb Ethernet Options 504 ms 40-50 ms Description Specifies the time before link_status is set to FAIL or OK. A link fails if the link_fail_ inhibit_time has expired before link_status is set to OK. The legal range is 500-510 ms. For more information, refer to "Clause 73 Auto Negotiation for Backplane Ethernet" in IEEE Std 802.3ap-2007.
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5-8 UG-01080 2015.01.19 1G/10GbE PHY Clock and Reset Interfaces 1G/10GbE PHY Clock and Reset Interfaces This topic illustrates the 1G/10GbE PHY clock and reset connectivity and describes the clock and reset signals. Use the Transceiver PHY Reset Controller IP Core to automatically control the transceiver reset sequence. This reset controller also has manual overrides for the TX and RX analog and digital circuits to allow you to reset individual channels upon reconfiguration.
UG-01080 2015.01.19 1G/10GbE PHY Data Interfaces 5-9 Table 5-6: Clock and Reset Signals Signal Name Direction Description rx_recovered_clk Output The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 156.25 MHz. For 10G PCS, its frequency is 257.8125 MHz. tx_clkout_1g Output GMII TX clock for the 1G TX and RX parallel data source interface. The frequency is 125 MHz.
5-10 UG-01080 2015.01.19 1G/10GbE PHY Data Interfaces Signal Name Direction Description xgmii_tx_dc[71:0] Input XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control. xgmii_tx_clk Input Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to xgmii_ rx_clk. The frequency is 156.25 MHz irrespective of 1588 being enabled or disabled. Driven from the MAC. xgmii_rx_dc[71:0] Output RX XGMII data and control for 8 lanes.
UG-01080 2015.01.19 XGMII Mapping to Standard SDR XGMII Data Signal Name Direction 5-11 Description led_disp_err Output Disparity error signal indicating a 10-bit running disparity error. Asserted for one rx_clkout_1g cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error. led_an Output Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
5-12 UG-01080 2015.01.19 Serial Data Interface Table 5-9: RX XGMII Mapping to Standard SDR XGMII Interface The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
UG-01080 2015.01.19 1G/10GbE Control and Status Interfaces Signal Name Direction 5-13 Description rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4. pll_locked Output When asserted, indicates the TX PLL is locked. rx_is_lockedtodata Output When asserted, indicates the RX channel is locked to input data. tx_cal_busy Output When asserted, indicates that the initial TX calibra‐ tion is in progress.
5-14 UG-01080 2015.01.19 Register Interface Signals Signal Name Direction Description rx_latency_adj_1g[21:0] Output When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent fractional number of clock cycles. Bits 10 to 21 represent number of clock cycles.
UG-01080 2015.01.19 1G/10GbE PHY Register Definitions Signal Name Direction 5-15 Description mgmt_write Input Write signal. Active high. mgmt_read Input Read signal. Active high. mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
5-16 UG-01080 2015.01.19 PMA Registers Addr 0xB1 Bit 0 R/W RO Name SEQ Link Ready Description When asserted, the sequencer is indicating that the link is ready. Related Information Avalon Interface Specifications PMA Registers The PMA registers allow you to reset the PMA and provide status information. Table 5-14: PMA Registers - Reset and Status The following PMA registers allow you to reset the PMA and provide status information.
UG-01080 2015.01.19 PCS Registers 5-17 Table 5-15: PMA Registers - TX and RX Serial Data Interface The following PMA registers allow you to customize the TX and RX serial data interface Address 0xA8 Bit R/W Name 0 RW tx_invpolarity 1 RW rx_invpolarity 2 RW rx_bitreversal_enable 3 RW 4 Description When set to 1, the TX interface inverts the polarity of the TX data. Inverted TX data is output from the 8B/10B encoder.
5-18 UG-01080 2015.01.19 1G/10 GbE GMII PCS Registers Addr Bit Acce ss Name Description 1 RO HI_BER High BER status. When set to 1, the PCS is reporting a high BER. When set to 0, the PCS is not reporting a high BER. 2 RO BLOCK_LOCK 0x82 3 RO TX_FULL When set to 1, the TX_FIFO is full. 4 RO RX_FULL When set to 1, the RX_FIFO is full. 5 RO RX_SYNC_HEAD_ERROR When set to 1, indicates an RX synchronization error.
UG-01080 2015.01.19 1G/10 GbE GMII PCS Registers Addr 0x94 Bit R/W Name 5 RW FD 6 RW HD 8:7 RW PS2,PS1 Description Full-duplex mode enable for the local device. Set to 1 for full-duplex support. Half-duplex mode enable for the local device. Set to 1 for half-duplex support. This bit should always be set to 0. Pause support for local device.
5-20 UG-01080 2015.01.19 PMA Registers Addr 0x95 Bit R/W Name 5 R FD 6 R HD 8:7 R PS2,PS1 Description Full-duplex mode enable for the link partner. This bit should always be 1 because only full duplex is supported. Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit should always be 0 because half-duplex mode is not supported. Specifies pause support for link partner.
UG-01080 2015.01.19 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE Address 0xA8 Bit R/W Name 0 RW tx_invpolarity 1 RW rx_invpolarity 2 RW rx_bitreversal_enable 3 RW 4 5-21 Description When set to 1, the TX interface inverts the polarity of the TX data. Inverted TX data is input to the 8B/10B encoder. When set to 1, the RX channels inverts the polarity of the received data. Inverted RX data is input to the 8B/10B decoder. When set to 1, enables bit reversal on the RX interface.
5-22 UG-01080 2015.01.19 1G/10GbE PHY Arbitration Logic Requirements Figure 5-4: Block Diagram for Reconfiguration Example Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 1G/10Gb Ethernet MAC1G/10Gb Ethernet MAC1G/10Gb Ethernet MAC Shared Across Multiple Channels 257.8 MHz TX XGMII Data @156.
UG-01080 2015.01.19 1G/10GbE PHY State Machine Logic Requirements 5-23 • Channel number—specifies the requested channel • Mode—specifies 1G or 10G mode for the corresponding channel 2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received. 3. Pass the selected channel and rate information to the state machine for processing. 4.
5-24 UG-01080 2015.01.19 Creating a 1G/10GbE Design Example 5-1: Edits to a MIF to Remove PMA Settings Creating a 1G/10GbE Design Here are the steps you must take to create a 1G/10GbE design using this PHY. 1. Generate the 1G/10GbE PHY with the required parameterization. 2. Generate a Transceiver Reconfiguration Controller with the correct number of reconfiguration interfaces based on the number of channels you are using. This controller is connected to all the transceiver channels.
UG-01080 2015.01.19 Dynamic Reconfiguration Interface Signals 5-25 8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock. 9. Instantiate the PHY in your design based on the required number of channels. 10.To complete the system, connect all the blocks. Dynamic Reconfiguration Interface Signals You can use the dynamic reconfiguration interface signals to dynamically change between 1G,10G data rates and AN or LT mode.
5-26 UG-01080 2015.01.19 Dynamic Reconfiguration Interface Signals Signal Name tap_to_upd[2:0] Direction Output Description Specifies the TX equalization tap to update to optimize signal quality. The following encodings are defined: • 3'b100: main tap • 3'b010: post-tap • 3'b001: pre-tap seq_start_rc Output When asserted, starts PCS reconfiguration. pcs_mode_rc[5:0] Output Specifies the PCS mode for reconfig using 1-hot encoding.
UG-01080 2015.01.19 1G/10 Gbps Ethernet PHY IP Core Signal Name Direction 5-27 Description mode_1g_10gbar Input This signal indicates the requested mode for the channel. A 1 indicates 1G mode and a 0 indicates 10G mode. This signal is only used when the sequencer which performs automatic speed detection is disabled. en_lcl_rxeq Output This signal is not used. You can leave this unconnected. rxeq_done Input Link training requires RX equalization to be complete.
5-28 UG-01080 2015.01.19 1G/10 Gbps Ethernet PHY IP Core Figure 5-5: Level Modules of the 1G/10GbE PHY MegaCore Function Altera Device with 10.3125+ Gbps Serial Transceivers 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257.8 MHz TX XGMII Data @156.
UG-01080 2015.01.19 5-29 Design Example Design Example Figure 5-6: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G) Ethernet Channels NF_DE_WRAPPER Test Harness Management Master ISSP Clock and Reset XGMII Test Harness Source XGMII Source JTAG-toAvalon-MM Master TH0_ADDR = 0xF nnn XGMII Sink XGMII Sink XGMII GEN XGMII GEN XGMII CHK XGMII CHK TH1_ADDR ... = 0xE nnn ...
5-30 UG-01080 2015.01.19 Simulation Support Simulation Support The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Altera-supported simulators for this Quartus II software release: • • • • ModelSim Verilog ModelSim VHDL VCS Verilog VCS VHDL Stratix® V devices also support NCSIM Verilog and NCSIM VHDL simulation. When you generate a 1G/ 10GbE or 10GBASE-KR PHY IP core, the Quartus II software optionally generates an IP functional simulation model.
UG-01080 2015.01.19 Acronyms Acronym Definition PMA Physical Medium Attachment. PMD Physical Medium Dependent. SGMII Serial Gigabit Media Independent Interface. WAN Wide Area Network. XAUI 10 Gigabit Attachment Unit Interface.
6 XAUI PHY IP Core 2015.01.19 UG-01080 Subscribe Send Feedback The Altera XAUI PHY IP Core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals. XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter. The XAUI IP Core accepts 72-bit data (single data rate– SDR XGMII) from the application layer at either 156.
6-2 UG-01080 2015.01.19 XAUI PHY Release Information XAUI PHY Release Information This section provides information about this release of the XAUI PHY IP Core. Table 6-1: XAUI Release Information Item Description Version 13.1 Release Date November 2013 Ordering Codes(4) P-XAUIPCS (primary)–Soft PCS IPR-XAUIPCS (renewal)–Soft PCS Product ID 00D7 Vendor ID 6AF7 XAUI PHY Device Family Support This section describes device family support for the IP core.
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6-4 UG-01080 2015.01.19 XAUI PHY General Parameters a. General Parameters b. Analog Parameters c. Advanced Options Parameters 5. Click Finish to generate your customized XAUI PHY IP Core. XAUI PHY General Parameters This section describes the settings available on General Options tab. Table 6-4: General Options Name Device family Value Arria II GX Description The target device family.
UG-01080 2015.01.19 XAUI PHY General Parameters Name XAUI interface type Value 6-5 Description Hard XAUI The following 3 interface types are available: Soft XAUI • Hard XAUI–Implements the PCS and PMA in hard logic. Available for Arria II, Cyclone IV, HardCopy IV, and Stratix IV devices. • Soft XAUI–Implements the PCS in soft logic and the PMA in hard logic. Available for HardCopy IV, Stratix IV, Arria V, Cyclone V, and Stratix V devices.
6-6 UG-01080 2015.01.19 XAUI PHY Analog Parameters Example 6-1 shows how to remove the restriction on logical lane 0 channel assignment in Stratix V devices by redefining the pma_bonding_master parameter using the Quartus II Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the XAUI instance name shown in quotation marks.
UG-01080 2015.01.19 XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices Name Value 6-7 Description Pre-emphasis pre-tap setting 0–7 Sets the amount of pre-emphasis on the TX buffer. Available for Stratix IV. Invert the pre-emphasis pre-tap polarity setting On Determines whether or not the preemphasis control signal for the pre-tap is inverted. If you turn this option on, the pre-emphasis control signal is inverted.
6-8 UG-01080 2015.01.19 Advanced Options Parameters Name Receiver static equalizer setting Value 0–15 Description This option sets the equalizer control settings. The equalizer uses a pass band filter. Specifying a low value passes low frequencies. Specifying a high value passes high frequencies. Available for HardCopy IV and Stratix IV devices. Advanced Options Parameters This section describes the settings available on the Advanced Options tab.
UG-01080 2015.01.19 XAUI PHY Configurations 6-9 XAUI PHY Configurations This section describes configurations of the IP core. The following figure illustrates one configuration of the XAUI IP Core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP Core, the transceiver reconfiguration control logic is included in the XAUI PHY IP Core. For Arria V, Cyclone V, and Stratix V devices the Transceiver Reconfiguration Controller must always be external.
6-10 UG-01080 2015.01.19 XAUI PHY Ports XAUI PHY Ports This section describes the ports for the IP core. Figure 6-3 illustrates the top-level signals of the XAUI PHY IP Core for the hard IP implementation. This variant is available for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV GX devices.Figure 6-4 illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementation.
UG-01080 2015.01.19 XAUI PHY Data Interfaces 6-11 The following figure illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementa‐ tion for both the single and DDR rates.
6-12 UG-01080 2015.01.19 SDR XGMII TX Interface For the DDR XAUI variant, the start of control character (0xFB) is aligned to either byte 0 or byte 5.
UG-01080 2015.01.19 SDR XGMII RX Interface 6-13 Table 6-7: SDR TX XGMII Interface Signal Name xgmii_tx_dc[71:0] Direction Output Description Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control. • • • • xgmii_tx_clk Input Lane 0–[7:0]/[8], [43:36]/[44] Lane 1–[16:9]/[17], [52:45]/[53] Lane 2–[25:18]/[26], [61:54]/[62] Lane 3–[34:27]/[35],[70:63]/[71] The XGMII SDR TX clock which runs at 156.25 MHz or 312.5 for the DDR variant.
6-14 UG-01080 2015.01.19 XAUI PHY Clocks, Reset, and Powerdown Interfaces Figure 6-8: Clock Inputs and Outputs for IP Core with Hard PCS phy_mgmt_clk XAUI Hard IP Core pll_ref_clk pll_inclk Hard PCS xgmii_tx_clk rx_cruclk PMA 4 tx_coreclk xgmii_rx_clk 4 coreclkout 4 x 3.
UG-01080 2015.01.19 XAUI PHY PMA Channel Controller Interface Signal Name Direction 6-15 Description xgmii_tx_clk Input The XGMII TX clock which runs at 156.25 MHz. Connect xgmii_tx_clk to xgmii_rx_clk to guarantee this clock is within 150 ppm of the transceiver reference clock. xgmii_rx_clk Output This clock is generated by the same reference clock that is used to generate the transceiver clock. Its frequency is 156.25 MHz.
6-16 UG-01080 2015.01.19 XAUI PHY Optional PMA Control and Status Interface XAUI PHY Optional PMA Control and Status Interface You can access the state of the optional PMA control and status signals available in the soft IP implemen‐ tation using the Avalon-MM PHY Management interface to read the control and status registers which are detailed in XAUI PHY IP Core Registers . However, in some cases, you may need to know the instantaneous value of a signal to ensure correct functioning of the XAUI PHY.
UG-01080 2015.01.19 XAUI PHY Optional PMA Control and Status Interface 6-17 neous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP Core. Table 6-13: Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices Name Direction Description rx_invpolarity[3:0] Input Dynamically reverse the polarity of every bit of the RX data at the input of the word aligner.
6-18 UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Name Direction Description rx_errdetect[7:0] Output Transceiver 8B/10B code group violation or disparity error indicator. If either signal is asserted, a code group violation or disparity error was detected on the associated received code group. Use the rx_disperr signal to determine whether this signal indicates a code group violation or a disparity error.
UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions 6-19 Table 6-14: Avalon-MM PHY Management Interface Signal Name Direction Input phy_mgmt_clk Description Avalon-MM clock input.
6-20 UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Word Addr 0x022 Bits [31:0] R/W R Register Name pma_tx_pll_is_locked Description Bit[P] indicates that the TX CMU PLL (P) is locked to the input reference clock. There is typically one pma_tx_pll_is_locked bit per system. This register is not available for Arria V, Arria V GZ, Cyclone V, or Stratix V devices.
UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Word Addr Bits R/W Register Name 0x061 [31:0] RW phy_serial_loopback 0x064 [31:0] RW pma_rx_set_locktodata 0x065 [31:0] RW pma_rx_set_locktoref 0x066 [31:0] RO pma_rx_is_lockedtodata 0x067 [31:0] RO pma_rx_is_lockedtoref 6-21 Description Writing a 1 to channel puts channel in serial loopback mode. For informa‐ tion about pre- or post-CDR serial loopback modes, refer to Loopback Modes.
6-22 UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Word Addr Bits R/W Register Name [31:16] - Reserved [15:8] patterndetect[7:0] 0x084 [7:0] Description When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary. The RX pattern detect signal is 2 bits wide per channel or 8 bits per XAUI link. Reading the value of the patterndetect registers clears the bits.
UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Word Addr Bits [31:8] R/W - [7:4] 0x086 [3:0] Register Name Reserved phase_comp_fifo_error[3:0] R, sticky rlv[3:0] 6-23 Description Indicates a RX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the value of the phase_comp_fifo_error register clears the bits. This register is only available in the hard XAUI implementation From block: RX phase compensation FIFO.
6-24 UG-01080 2015.01.19 XAUI PHY Register Interface and Register Descriptions Word Addr Bits [31:8] R/W - [7:4] 0x088 [3:0] Register Name Reserved rmfifofull[3:0] R, sticky rmfifoempty[3:0] Description When asserted, indicates that rate match FIFO is full (20 words). Bits 0-3 correspond to lanes 0-3, respectively. Reading the value of the rmfifofull register clears the bits. This register is only available in the hard XAUI implementation From block: Rate match FIFO.
UG-01080 2015.01.19 XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX 6-25 • Transceiver Architecture in Stratix V Devices XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX The Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX use the ALTGX_RECONFIG Mega function for transceiver reconfiguration.
6-26 UG-01080 2015.01.19 Logical Lane Assignment Restriction Example 6-2: Informational Messages for the Transceiver Reconfiguration Interface PHY IP will require 8 reconfiguration interfaces for connection to the external reconfiguration controller.Reconfiguration interface offsets 0-3 are connected to the transceiver channels.Reconfiguration interface offsets 4-7 are connected to the transmit PLLs.
UG-01080 2015.01.19 SDC Timing Constraints 6-27 Table 6-17: Reconfiguration Interface Signal Name reconfig_to_xcvr [(70)1:0] reconfig_from_xcvr [(46) -1:0] Direction Description Input Reconfiguration signals from the Transceiver Reconfigu‐ ration Controller. grows linearly with the number of reconfiguration interfaces. initially includes the total number transceiver channels and TX PLLs before optimization/merging.
7 Interlaken PHY IP Core 2015.01.19 UG-01080 Subscribe Send Feedback The Altera Interlaken PHY IP Core implements Interlaken Protocol Specification, Rev 1.2. Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. It supports multiple instances, each with 1 to 24 lanes running at 10.3125 Gbps or greater in Arria V GZ and Stratix V devices. The key advantages of Interlaken are scalability and its low I/O count compared to earlier protocols such as SPI 4.2.
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UG-01080 2015.01.19 Parameterizing the Interlaken PHY 7-3 Parameterizing the Interlaken PHY The Interlaken PHY IP Core is available when you select the Arria V GZ or Stratix V devices. Complete the following steps to configure the Interlaken PHY IP Core in the MegaWizard Plug-In Manager: 1. 2. 3. 4. Under Tools > IP Catalog, select the device family of your choice. Under Tools > Interface Protocols > Interlaken, select Interlaken PHY.
7-4 UG-01080 2015.01.19 Interlaken PHY General Parameters Parameter Metaframe length in words Value 5-8191 Description Specifies the number of words in a metaframe. The default value is 2048. Although 5 -8191 words are valid metaframe length values, the current Interlaken PHY IP Core implementation requires a minimum of 128 Metaframe length for good, stable performance. In simulation, Altera recommends that you use a smaller metaframe length to reduce simulation times.
UG-01080 2015.01.19 Interlaken PHY Optional Port Parameters Parameter Base data rate Value 1 × Lane rate 2 × Lane rate 3 × Lane rate 7-5 Description This option allows you to specify a Base data rate to minimize the number of PLLs required to generate the clocks necessary for data transmission at different frequencies. Depending on the Lane rate you specify, the default Base data rate can be either 1, 2, or 4 times the Lane rate; however, you can change this value.
7-6 UG-01080 2015.01.19 Interlaken PHY Interfaces Click on the appropriate link to specify the analog options for your device: Related Information • Analog Settings for Arria V GZ Devices on page 19-11 • Analog Settings for Stratix V Devices on page 19-34 Interlaken PHY Interfaces This section describes the Interlaken PHY interfaces.
UG-01080 2015.01.19 Interlaken PHY Avalon-ST TX Interface 7-7 Interlaken PHY Avalon-ST TX Interface This section lists the signals in the Avalon-ST TX interface. Table 7-4: Avalon-ST TX Signals Signal Name Direction Description tx_parallel_data[63:0] Input Avalon-ST data bus driven from the FPGA fabric to the TX PCS. This input should be synchronized to the tx_coreclkin clock domain. tx_parallel_data[64] Input Indicates whether tx_parallel_data[63:0] represents control or data.
7-8 UG-01080 2015.01.19 Interlaken PHY Avalon-ST TX Interface Signal Name tx_parallel_data[65] Direction Input Description When asserted, indicates that tx_parallel_data [63:0] is valid and is ready to be written into the TX FIFO. When deasserted, indicates that tx_parallel_ data[63:0] is invalid and is not written into the TX FIFO. This signal is the data valid or write enable port of the TX FIFO. This input must be synchronized to the tx_coreclkin clock domain.
UG-01080 2015.01.19 Interlaken PHY Avalon-ST TX Interface Signal Name Direction 7-9 Description multi-lane configurations, the tx_datain_bp signals must be logically Ored. The latency on this Avalon-ST interface is 0 cycles. The Interlaken MAC must only drive valid user data on tx_parallel_ data[64] and tx_parallel_data[63:0] data bus as soon as tx_ready and tx_sync_done are both asserted.
7-10 UG-01080 2015.01.19 Interlaken PHY Avalon-ST RX Interface Signal Name Direction Description pll_locked Output In multilane Interlaken designs, this signal is the bitwise AND of the individual lane pll_locked signals. This output is synchronous to the phy_mgmt_clk clock domain. tx_sync_done Output When asserted, indicates that all tx_parallel_data lanes are synchronized and ready for valid user data traffic.
UG-01080 2015.01.19 Interlaken PHY Avalon-ST RX Interface Signal Name rx_parallel_data [64] Direction Output 7-11 Description When asserted, indicates that rx_parallel_data[63:0] is valid. When deasserted, indicates the rx_parallel_data [63:0] is invalid. This output is synchronous to the rx_ coreclkin clock domain. The Interlaken PCS implements a gearbox between the PMA and PCS interface. The rx_parallel_data[64] port is deasserted whenever the gearbox is in the invalid region.
7-12 UG-01080 2015.01.19 Interlaken PHY Avalon-ST RX Interface Signal Name rx_parallel_data [67] rx_parallel_data [68] Direction Description Output When asserted, indicates an RX FIFO overflow error. Output When asserted, indicates that the RX FIFO is partially empty and is still accepting data from the frame synchronizer. This signal is asserted when the RX FIFO fill level is below the rx_ fifo_pempty threshold. This output is synchronous to the rx_ coreclkin clock domain.
UG-01080 2015.01.19 Interlaken PHY Avalon-ST RX Interface Signal Name rx_parallel_data [70] Direction Output 7-13 Description When asserted, indicates that the RX frame synchronization state machine has found and received 4 consecutive, valid synchronization words. The frame synchronization state machine requires 4 consecutive synchronization words to exit the presync state and enter the synchronized state. You should only use this optional signal as a secondary status flag.
7-14 UG-01080 2015.01.19 Interlaken PHY TX and RX Serial Interface Signal Name rx_dataout_bp Direction Input Description When asserted, enables reading of data from the RX FIFO. This signal functions as a read enable. The RX interface has a ready latency of 1 cycle so that rx_paralleldata[63:0] and rx_ paralleldata[65] are valid the cycle after rx_dataout_ bp is asserted. In multi-lane configurations, the rx_dataout_bp port signals must not be logically tied together.
UG-01080 2015.01.19 Interlaken Optional Clocks for Deskew 7-15 Table 7-7: PLL Interface Signal Name pll_ref_clk Direction Input Description Reference clock for the PHY PLLs. Refer to the Lane rate entry in the Table 7-2table for required frequen‐ cies. Custom, user-defined, data rates are now supported. However, the you must choose a lane data rate that results in standard board oscillator reference clock frequency to drive the pll_ref_clk and meet jitter requirements.
7-16 UG-01080 2015.01.19 Interlaken PHY Register Interface and Register Descriptions Interlaken PHY Register Interface and Register Descriptions This section describes the register interface and register descriptions. The Avalon-MM PHY management interface provides access to the Interlaken PCS and PMA registers, resets, error handling, and serial loopback controls. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.
UG-01080 2015.01.19 Interlaken PHY Register Interface and Register Descriptions 7-17 Table 7-10: Interlaken PHY Registers Word Addr Bits R/W Register Name Description PMA Common Control and Status Registers 0x022 [
-1:0] RO pma_tx_pll_is_locked If
is the PLL number, Bit[
] indicates that the TX CMU PLL (
) is locked to the input reference clock. There is typically one pma_tx_pll_is_ locked bit per system.
7-18 UG-01080 2015.01.19 Interlaken PHY Register Interface and Register Descriptions Word Addr Bits R/W Register Name Description The Interlaken PHY IP requires the use of the embedded reset controller to initiate the correct the reset sequence. A hard reset to phy_mgmt_clk_reset and mgmt_rst_reset is required for Interlaken PHY IP. Altera does not recommend use of a soft reset or the use of these reset register bits for Interlaken PHY IP.
UG-01080 2015.01.19 Interlaken PHY Register Interface and Register Descriptions Word Addr Bits R/W 0x065 [31:0] RW 0x066 [31:0] RO 00x067 [31:0] RO 0x080 [31:0] WO Register Name pma_rx_set_locktoref pma_rx_is_ lockedtodata pma_rx_is_ lockedtoref indirect_addr 7-19 Description When set, programs the RX CDR PLL to lock to the reference clock. Bit corresponds to channel . By default, the Interlaken PHY IP configures the CDR PLL in Auto lock Mode.
7-20 UG-01080 2015.01.19 Why Transceiver Dynamic Reconfiguration Why Transceiver Dynamic Reconfiguration Dynamic reconfiguration is necessary to calibrate transceivers to compensate for variations due to PVT. As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges.
UG-01080 2015.01.19 Interlaken PHY TimeQuest Timing Constraints Signal Name reconfig_from_xcvr [(46)-1:0] Direction Output 7-21 Description Reconfiguration signals to the Transceiver Reconfiguration Controller. grows linearly with the number of reconfigura‐ tion interfaces. initially includes the total number transceiver channels before optimization/merging. Note: Transceiver dynamic reconfiguration requires that you assign the starting channel number.
PHY IP Core for PCI Express (PIPE) 8 2015.01.19 UG-01080 Subscribe Send Feedback The Altera PHY IP Core for PCI Express (PIPE) implements physical coding sublayer (PCS) and physical media attachment (PMA) modules for Gen1, Gen2, and Gen3 data rates. The Gen1 and Gen2 datapaths are compliant to the Intel PHY I nterface for PCI Express (PIPE) Architec‐ ture PCI Express 2.0 specification. The Gen3 datapath is compliant to the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification.
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UG-01080 2015.01.19 PHY for PCIe (PIPE) Device Family Support 8-3 • Stratix V Hard IP for PCI Express IP Core User Guide • Transceiver Configurations in Arria V GZ Devices or Transceiver Configurations in Stratix V Devices PHY for PCIe (PIPE) Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
8-4 UG-01080 2015.01.19 PHY for PCIe (PIPE) General Options Parameters Table 8-2: PHY IP Core for PCI Express General Options Name Device family Value Stratix V Arria V GZ Description Supports all Arria V and Stratix V devices. Arria V GX Arria V GT Arria V SX Arria V ST Number of lanes 1, 2, 4, 8 The total number of duplex lanes. Protocol version Gen1 (2.5 Gbps) The Gen1 and Gen2 implement the Intel PHY Interface for PCI Express (PIPE) Architecture PCI Express 2.0 specification.
UG-01080 2015.01.19 PHY for PCIe (PIPE) General Options Parameters Name Gen1 and Gen2 PLL type Value CMU ATX 8-5 Description You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies.
8-6 UG-01080 2015.01.19 PHY for PCIe (PIPE) Interfaces • PHY Interface for the PCI Express Architecture PCI Express 3.0 PHY for PCIe (PIPE) Interfaces This section describes interfaces of the PHY IP Core for PCI Express (PIPE). The following figure illustrates the top-level pinout of the PHY IP Core for PCI Express PHY.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Input Data from the PHY MAC 8-7 For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook. Related Information Component Interface Tcl Reference PHY for PCIe (PIPE) Input Data from the PHY MAC Input data signals are driven from the PHY MAC to the PCS. This interface is compliant to the appropriate PIPE interface specification.
8-8 UG-01080 2015.01.19 PHY for PCIe (PIPE) Input Data from the PHY MAC Signal Name Direction Description tx_blk_start Input For Gen3, specifies start block byte location for TX data in the 128-bit block data. Used when the interface between the PCS and PHY MAC is 32 bits. Not used for the Gen1 and Gen2 data rates. tx_sync_hdr[1:0] Input For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Input Data from the PHY MAC Signal Name pipe_g3_txdeemph[17:0] Direction Input 8-9 Description For Gen3, selects the transmitter de-emphasis. The 18 bits specify the following coefficients: • [5:0]: C-1 • [11:6]: C0 • [17:12]: C+1 Refer toTable 8-4 for presets to TX de-emphasis mappings. In Gen3 capable designs, the TX deemphasis for Gen2 data rates is always -6 dB. The TX deemphasis for Gen1 data rate is always -3.5 dB.
8-10 UG-01080 2015.01.19 PHY for PCIe (PIPE) Input Data from the PHY MAC Signal Name rx_eidleinfersel[3-1:0] Direction Input Description When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Output Data to the PHY MAC 8-11 PHY for PCIe (PIPE) Output Data to the PHY MAC This section describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC. This interface is compliant to the appropriate PIPE interface specification. Table 8-5: Avalon-ST RX Inputs Signal Name Direction pipe_rxdata[[(31,16or 8)1:0] Output Description This is RX parallel data driven from the PCS to the MAC PHY.
8-12 UG-01080 2015.01.19 PHY for PCIe (PIPE) Output Data to the PHY MAC Signal Name Direction Description pipe_rx_data_valid Output For Gen3, this signal is deasserted by the PHY to instruct the MAC to ignore pipe_rxdata for one clock cycle. A value of 1 indicates the MAC should use the data. A value of 0 indicates the MAC should not use the data. pipe_rxvalid[-1:0] Output Asserted when RX data and control are valid.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Clocks 8-13 PHY for PCIe (PIPE) Clocks This section describes the clock ports. Table 8-6: Clock Ports Signal Name Direction Description pll_ref_clk Input This is the 100 MHz input reference clock source for the PHY TX and RX PLL. You can optionally provide a 125 MHz input reference clock by setting the PLL reference clock frequency parameter to 125 MHz as described in PHY IP Core for PCI Express General Options.
8-14 UG-01080 2015.01.19 PHY for PCIe (PIPE) Optional Status Interface Add the following command to force Timequest analysis at 62.5 MHz. create_generated_clock -name clk_g1 -source [get_ports {pll_refclk}] \ -divide_by 8 -multiply_by 5 -duty_cycle 50 -phase 0 -offset 0 [get_nets \ {*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs| \ ch[*].
UG-01080 2015.01.19 PHY for PCIe (PIPE) Register Interface and Register Descriptions 8-15 Table 8-9: Transceiver Differential Serial Interface Signal Name Direction Description rx_serial_data[-1:0] Input Receiver differential serial input data, is the number of lanes. tx_serial_data[-1:0] Output Transmitter differential serial output data is the number of lanes.
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UG-01080 2015.01.19 PHY for PCIe (PIPE) Register Interface and Register Descriptions Signal Name Direction 8-17 Description phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
8-18 UG-01080 2015.01.19 PHY for PCIe (PIPE) Register Interface and Register Descriptions Word Addr Bits R/W Register Name Description [31:0] RW reset_fine_control You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Transceiver PHY Top-Level Modules, performs a standard reset sequence at power on and whenever the phy_mgmt_ clk_reset is asserted. Bits [31:4, 0] are reserved.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Register Interface and Register Descriptions Word Addr Bits R/W Register Name 0x064 [31:0] RW pma_rx_set_locktodata 0x065 [31:0] RW pma_rx_set_locktoref 0x066 [31:0] R pma_rx_is_lockedtodata 0x067 [31:0] R pma_rx_is_lockedtoref 8-19 Description When set, programs the RX CDR PLL to lock to the incoming data. Bit corresponds to channel . When set, programs the RX CDR PLL to lock to the reference clock. Bit corresponds to channel .
8-20 UG-01080 2015.01.19 PHY for PCIe (PIPE) Register Interface and Register Descriptions Word Addr Bits R/W Register Name Description [31:6] RW Reserved — [5:1] tx_bitslipboundary_select Sets the number of bits the TX block needs to slip the output. Used for very latency sensitive protocols. RW 0x083 From block: TX bit-slipper. 0x084 [31:1] RW Reserved — [31:4] RW Reserved — [3] rx_bitslip When set, the word alignment logic operates in bitslip mode.
UG-01080 2015.01.19 PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate Word Addr Bits R/W [31:20 R ] [19:16 R ] [15:12 R ] Register Name 8-21 Description Reserved — rx_rlv When set, indicates a run length violation. From block: Word aligner. rx_patterndetect When set, indicates that RX word aligner has achieved synchronization. From block: Word aligner. [11:8] R 0x086 rx_disperr When set, indicates that the received 10-bit code or data group has a disparity error.
8-22 Phase 0 UG-01080 2015.01.19 “Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification, Rev. 3.0 provides detailed information about the four-stage link equalization procedure. A new LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional; however, the link must progress through all four phases, even if no adjustments occur.
UG-01080 2015.01.19 Phase 3 (Optional) 8-23 The tuning sequence typically includes the following steps: 1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port. 2. The circuitry in the Endpoint receiver determines the BER and calculates the next set of transmitter coefficients using FS and LF and embeds this information in the Training Sets for the Link Partner to apply to its transmitter.
8-24 UG-01080 2015.01.19 PHY for PCIe (PIPE) Dynamic Reconfiguration some instances you may want to override the specified four-stage link equalization procedure to dynamically tune PMA settings. Follow these steps to override Gen3 equalization: 1. Connect the Transceiver Reconfiguration Controller IP Core to your PHY IP Core for PCI Express as shown in PCI Express PIPE IP Core Top-Level Modules. 2.
UG-01080 2015.01.19 Logical Lane Assignment Restriction 8-25 Table 8-12: Reconfiguration Interface Signals Signal Name reconfig_to_xcvr [701:0] reconfig_from_xcvr [461:0] Direction Description Input Reconfiguration signals from the Transceiver Reconfigu‐ ration Controller. grows linearly with the number of reconfiguration interfaces. Output Reconfiguration signals to the Transceiver Reconfigura‐ tion Controller. grows linearly with the number of reconfiguration interfaces.
9 Custom PHY IP Core 2015.01.19 UG-01080 Subscribe Send Feedback The Altera Custom PHY IP Core is a generic PHY that you can customize for use in Arria V, Cyclone V, or Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.611–6.5536 Gbps for Arria V GX devices, 0.611–10.3125 Gbps in Arria V GT devices, 0.622–9.8304 Gbps in Arria V GZ devices, 0.611–3.125 Gbps for Cyclone V GX devices, 0.611– 5.
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UG-01080 2015.01.19 Parameterizing the Custom PHY 9-3 Table 9-2: Custom PHY IP Core Performance and Resource Utilization—Stratix V GT Device Channels Combinational ALUTs Logic Registers (Bits) 1 142 154 4 244 364 Parameterizing the Custom PHY Complete the following steps to configure the Custom PHY IP Core: 1. 2. 3. 4. Under Tools > IP Catalog, select the device family of your choice. Under Tools > IP Catalog > Interfaces > Transceiver PHY, select Custom PHY .
9-4 UG-01080 2015.01.19 General Options Parameters Name Bonding mode Value Non-bonded or x1 Bonded or xN fb_compensation Description Select Non-bonded or x1 to use separate clock sources for each channel. (This option is available for Cyclone V and Arria V devices.) If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, merges all the PLLs that meet PLL merging requirements.
UG-01080 2015.01.19 General Options Parameters Name PCS-PMA interface width PLL type Value 8, 10, 16, 20 CMU ATX 9-5 Description The PCS-PMA interface width depends on the FPGA fabric transceiver interface width and whether 8B/10B is enabled.
9-6 UG-01080 2015.01.19 General Options Parameters Name Base data rate Value 1 × Data rate 2 × Data rate 4 × Data rate Input clock frequency Variable Description The base data rate is the frequency of the clock input to the PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block.
UG-01080 2015.01.19 Word Alignment Parameters Name Value Enable embedded reset control 9-7 Description On/Off When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogreset , rx_analogreset, tx_digitalreset, rx_digitalreset, and pll_powerdown which are top-level ports of the Custom Transceiver PHY. You may also use the Transceiver PHY Reset Controller' to reset the transceivers.
9-8 UG-01080 2015.01.19 Word Alignment Parameters Table 9-5: Word Aligner Options Name Word alignment mode Value Description Manual In this mode you enable the word alignment function by asserting rx_enapatternalign using the Avalon-MM interface. When the PCS exits reset, the word aligner automati‐ cally performs an initial alignment to the specified word alignment pattern when the interface between the PCS and PMA is 16 or 20 bits.
UG-01080 2015.01.19 Rate Match FIFO Parameters Name Value 9-9 Description Enable run length violation checking On/Off If you turn this option on, you can specify the run length which is the maximum legal number of contiguous 0s or 1s. Run length 40-640 Specifies the threshold for a run-length violation.
9-10 UG-01080 2015.01.19 8B/10B Encoder and Decoder Parameters reference clock frequency is greater than the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. If you enable the rate match FIFO, the MegaWizard Plug-In Manager provides options to enter the rate match insertion and deletion patterns.
UG-01080 2015.01.19 Byte Order Parameters 9-11 Table 9-8: 8B/10B Options Name Value Enable 8B/10B decoder/encoder On/Off Enable manual disparity control On/Off Description Enable this option if your application requires 8B/10B encoding and decoding. This option on adds the tx_datak , rx_datak , and rx_runningdisp signals to your transceiver. When enabled, you can use the tx_ forcedisp signal to control the disparity of the 8B/10B encoder.
9-12 UG-01080 2015.01.19 Byte Order Parameters Table 9-9: Byte Order Options Name Enable byte ordering block Value On/Off Description Turn this option on if your application uses serialization to create a datapath that is larger than 1 symbol.
UG-01080 2015.01.19 Byte Order Parameters Name Enable byte ordering block manual control Byte ordering pattern Value 9-13 Description On/Off Turn this option on to choose manual control of byte ordering. This option creates the rx_ enabyteord signal. A byte ordering operation occurs whenever rx_enabyteord is asserted. To perform multiple byte ordering operations, deassert and reassert rx_ enabyteord. Depends on configuration Specifies the pattern that identifies the SOP.
9-14 UG-01080 2015.01.19 PLL Reconfiguration Parameters Name Byte ordering pad pattern Value 00000000 Description Specifies the pad pattern that is inserted to align the SOP.
UG-01080 2015.01.19 PLL Reconfiguration Parameters 9-15 Name Value Description Number of reference clocks 1-5 Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index 0-3 Specifies the index for the TX PLL that should be instantiated at startup. Logical index 0 corresponds to TX PLL0, and so on.
9-16 UG-01080 2015.01.19 Analog Parameters Name Enable channel interface Value Description On/Off Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_ data and rx_parallel_data buses increases in the following way. • n The tx_parallel_data bus is 44 bits per lane; however, only the low-order number of bits specified by the FPGA fabric transceiver interface width contain valid data for each lane.
UG-01080 2015.01.19 Presets for Ethernet Parameter Name GIGE-1.25 Gbps GIGE-2.50 Gbps 10 10 Data rate 1250 Mbps 3125 Mbps Input clock frequency 62.5 MHz 62.
9-18 UG-01080 2015.01.19 Presets for Ethernet Parameter Name GIGE-1.25 Gbps GIGE-2.
UG-01080 2015.01.
9-20 UG-01080 2015.01.19 Data Interfaces Table 9-12: Avalon-ST TX Interface Signals Signal Name tx_parallel_data[( 43:0] Direction Input Description This is TX parallel data driven from the MAC. The ready latency on this interface is 0, so that the PHY must be able to accept data as soon as it comes out of reset. The bits of each 11-bit word have the following definitions when you enable 8B/10B encoding: • tx_parallel_data[7:0]: TX data bus. • tx_parallel_data[8]: TX data control character.
UG-01080 2015.01.19 Data Interfaces 9-21 Table 9-13: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 11-bit data words with and without the byte deserializer for single- and double-word FPGA fabric to PCS interface widths. The byte serializer allows the PCS to operate at twice the data width of the PMA . This feature allows the PCS to run at a lower frequency and accommodates a wider range of FPGA interface widths.
9-22 UG-01080 2015.01.19 Data Interfaces Table 9-14: Avalon-ST RX Interface Signals These signals are driven from the PCS to the MAC. This is an Avalon source interface. Signal Name rx_parallel_data[63:0] Direction Output Description This is RX parallel data driven from the Custom PHY IP Core. The ready latency on this interface is 0, so that the MAC must be able to accept data as soon as the PHY comes out of reset. Data driven from this interface is always valid.
UG-01080 2015.01.19 Clock Interface Signal Name Direction 9-23 Description rx_clkout[< n >-1:0] Output This is the clock for the RX parallel data source interface. rx_datak[< n >(/)-1:0] Output Data and control indicator for the source data. When 0, indicates that rx_parallel_data is data, when 1, indicates that rx_parallel_data is control. Output This status signal indicates the disparity of the incoming data.
9-24 UG-01080 2015.01.19 Optional Status Interface Table 9-17: Clock Signals Signal Name Direction Description pll_ref_clk Input Reference clock for the PHY PLLs. Frequency range is 50-700 MHz. rx_coreclkin[-1:0] Input This is an optional clock to drive the coreclk of the RX PCS.
UG-01080 2015.01.19 Optional Status Interface Signal Name Direction 9-25 Signal Name Output When asserted, indicates that a received 10-bit code group has an 8B/ 10B code violation or disparity error. Output Indicates presence or absence of synchronization on the RX interface. Asserted when word aligner identifies the word alignment pattern or synchronization code groups in the received data stream. This signal is optional.
9-26 UG-01080 2015.01.19 Optional Reset Control and Status Interface Signal Name Direction Signal Name rx_rmfifodatainserted[-1:0] Output When asserted, indicates that the RX rate match block inserted an ||R|| column. rx_rmfifodatadeleted[-1:0] Output When asserted, indicates that the RX rate match block deleted an ||R|| column. rx_rlv[ -1:0] Output When asserted, indicates a run length violation.
UG-01080 2015.01.19 Register Interface and Register Descriptions Signal Name tx_cal_busy[-1:0] Direction Output Description When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes. rx_digitalreset[-1:0] Input When asserted, resets the RX PCS.
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UG-01080 2015.01.19 Custom PHY IP Core Registers Signal Name Direction Description Output Output data. phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. phy_mgmt_readdata[31:0] Output phy_mgmt_waitrequest 9-29 When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
9-30 UG-01080 2015.01.19 Reset Controls –Manual Mode Word Addr 0x042 Bits R/W Register Name Description W reset_control (write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. R reset_status (read) Reading bit 0 returns the status of the reset controller TX ready bit.
UG-01080 2015.01.19 PMA Control and Status Registers Word Addr Bits R/W Register Name [2] RW reset_rx_analog [1] RW reset_tx_digital 9-31 Description Writing a 1 causes the internal RX analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition. Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask.
9-32 UG-01080 2015.01.19 Custom PCS Custom PCS Table 9-25: Custom PCS Word Addr Bits R/W Register Name 0x080 [31:0] RW Lane or group number [5:1] R rx_bitslipboundaryselect out 0x081 Description Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non-bonded applications, this is the logical lane number.
UG-01080 2015.01.19 SDC Timing Constraints Word Addr Bits R/W [3] RW Register Name rx_bitslip 9-33 Description Every time this register transitions from 0 to 1, the RX data slips a single bit. To block: Word aligner. [2] RW rx_bytereversal_enable When set, enables byte reversal on the RX interface. To block: Byte deserializer. 0x085 [1] RW rx_bitreversal_enable When set, enables bit reversal on the RX interface. To block: Word aligner.
9-34 UG-01080 2015.01.19 Dynamic Reconfiguration Example 9-1: Informational Messages for the Transceiver Reconfiguration Interface PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller. Reconfiguration interface offset 0 is connected to the transceiver channel. Reconfiguration interface offset 1 is connected to the transmit PLL. Table 9-26: Reconfiguration Interface This interface uses the Avalon-MM PHY Management interface clock.
Low Latency PHY IP Core 10 2015.01.19 UG-01080 Subscribe Send Feedback The Altera Low Latency PHY IP Core receives and transmits differential serial data, recovering the RX clock from the RX input stream. The PMA connects to a simplified PCS, which contains a phase compensation FIFO.
10-2 UG-01080 2015.01.19 Device Family Support Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device. The following table shows the level of support offered by the Low Latency PHY IP Core for Altera device families.
UG-01080 2015.01.19 Parameterizing the Low Latency PHY Implementa‐ tion Number of Lanes Serialization Factor Worst-Case Frequency Combinational ALUTs Dedicated Registers 10-3 Memory Bits 6 Gbps (8 Gbps datapath) 1 32 or 40 607.16 113 93 0 6 Gbps (8 Gbps datapath) 4 32 or 40 639.8 142 117 0 6 Gbps (8 Gbps datapath) 10 32 or 40 621.89 193 171 0 3 Gbps (8 Gbps datapath) 1 8, 10, 16, or 20 673.4 114 93 0 3 Gbps (8 Gbps datapath) 4 8, 10, 16, or 20 594.
10-4 UG-01080 2015.01.19 General Options Parameters • General Options Parameters on page 10-4 • Additional Options Parameters on page 10-7 • PLL Reconfiguration Parameters on page 10-10 • Low Latency PHY Analog Parameters on page 10-12 5. Click Finish to generate your parameterized Low Latency PHY IP Core.
UG-01080 2015.01.19 General Options Parameters Name Bonding mode Value 10-5 Description ×N Select ×N to use the same clock source for up to 6 channels in a single transceiver bank, fb_compensation resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding. In addition, you must place logical channel 0 in either physical channel 1 or 4. Physical channels 1 and 4 are indirect drivers of the ×N clock network.
10-6 UG-01080 2015.01.19 General Options Parameters Name Value Description Data rate Device dependent Specifies the data rate in Mbps. Refer to Stratix V Device Datasheet for the data rate ranges of datapath. Base data rate 1 × Data rate Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block.
UG-01080 2015.01.19 Additional Options Parameters FPGA Fabric Transceiver Interface Width 10-7 PCS-PMA Interface Width Standard Datapath 10G Datapath tx_clkout and rx_clkout frequency 50 — 40 data rate/50 (6) 64 — 32 data rate/32 (7) 64 — 64 data rate/64 66 — 40 data rate/66 Related Information • Stratix V Device Datasheet • Transceiver Clocking in Stratix V Devices Additional Options Parameters The parameters on the Additional Options tab control clocking and datapath options.
10-8 UG-01080 2015.01.19 Additional Options Parameters The following table describes the options available on the Additional Options tab: Table 10-5: Additional Options Name Enable tx_coreclkin Value On/Off Description When you turn this option on, tx_coreclkin connects to the write clock of the TX phase compensation FIFO and you can clock the parallel TX data generated in the FPGA fabric using this port.
UG-01080 2015.01.19 Additional Options Parameters Name Enable TX bitslip Value On/Off 10-9 Description The bit slip feature allows you to slip the transmitter side bits before they are sent to the gearbox. The maximum number of bits slipped is equal to the ((FPGA fabric-to-transceiver interface width) – 1). For example, if the FPGA fabric-to-transceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits. Each channel has 5 bits to determine the number of bits to slip.
10-10 UG-01080 2015.01.19 PLL Reconfiguration Parameters Name Avalon data interfaces Value On/Off Description When you turn this option On, the order of symbols is changed. This option is typically required if you are planning to import your Low Latency Transceiver PHY IP Core into a Qsys system.
UG-01080 2015.01.19 PLL Reconfiguration Parameters Name Number of TX PLLs Value 1–4 10-11 Description Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network.
10-12 UG-01080 2015.01.19 Low Latency PHY Analog Parameters TX PLL (0–3) (Refer to Low Latency PHY General Options for a detailed explanation of these parameters.) Reference clock frequency Variable Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency.
UG-01080 2015.01.19 10-13 Low Latency PHY Interfaces Related Information Analog Parameters Set Using QSF Assignments on page 19-1 Low Latency PHY Interfaces The following figure illustrates the top-level signals of the Custom PHY IP Core.
10-14 UG-01080 2015.01.19 Low Latency PHY Data Interfaces Table 10-7: Avalon-ST interface Signal Name Direction Description tx_parallel_data[-1:0] Input This is TX parallel data driven from the MAC FPGA fabric. The ready latency on this interface is 0, so that the PCS in LowLatency Bypass Mode or the MAC in PMA Direct mode must be able to accept data as soon as it comes out of reset. tx_clkout[-1:0] Output This is the clock for TX parallel data.
UG-01080 2015.01.19 Optional Status Interface 10-15 Optional Status Interface The following table describes the signals that comprise the optional status interface: Table 10-9: Optional Status Interface Signal Name Direction Description rx_is_lockedtodata[-1:0] Output When asserted, indicates that the RX CDR is locked to incoming data. This signal is optional. If latency is not critical, you can read the value of this signal from the Rx_is_lockedtodata register.
10-16 UG-01080 2015.01.19 Optional Reset Control and Status Interface Signal Name pll_ref_clk Direction Input Description Reference clock for the PHY PLLs. The frequency range is 60–700 MHz. Optional Reset Control and Status Interface The following table describes the signals in the optional reset control and status interface. These signals are available if you do not enable the embedded reset controller.
UG-01080 2015.01.19 10-17 Register Interface and Register Descriptions Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the Low Latency PHY PCS and PMA registers that control the TX and RX channels, the PMA powerdown, PLL registers, and loopback modes. The following figure provides a high level view of this hardware.
10-18 UG-01080 2015.01.19 Register Interface and Register Descriptions Signal Name Direction Description phy_mgmt_writedata[31:0] Input Input data. phy_mgmt_readdata[31:0] Output Output data. phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. For more information about the Avalon-MM and Avalon-ST protocols, including timing diagrams, refer to the Avalon Interface Specifications .
UG-01080 2015.01.19 Dynamic Reconfiguration Word Addr Bits R/W Register Name 10-19 Description Reset Control Registers–Automatic Reset Controller 0x063 [31:0] R 0x064 [31:0] RW 0x065 [31:0] RW 0x066 [31:0] RO 0x067 [31:0] RO pma_rx_signaldetect pma_rx_set_ locktodata pma_rx_set_locktoref pma_rx_is_lockedtodata pma_rx_is_ lockedtoref When channel =1, indicates that receive circuit for channel senses the specified voltage exists at the RX input buffer.
10-20 UG-01080 2015.01.19 SDC Timing Constraints Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfigu‐ ration Controller to PHY IP Connectivity. The following table describes the signals in the reconfiguration interface. This interface uses a clock provided by the reconfiguration controller.
UG-01080 2015.01.19 Simulation Files and Example Testbench 10-21 Related Information SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths. Simulation Files and Example Testbench Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your Low Latency PHY IP Core.
Deterministic Latency PHY IP Core 11 2015.01.19 UG-01080 Subscribe Send Feedback Deterministic latency enables accurate delay measurements and known timing for the transmit (TX) and receive (RX) datapaths as required in applications such as wireless communication systems, emerging Ethernet standards, and test and measurement equipment. The Deterministic Latency PHY IP Core support 1-32 lanes with a continuous range of data rates from 611–6144 Mbps for Arria V devices, 0.6222–6.
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UG-01080 2015.01.19 Achieving Deterministic Latency Data Rate (Mbps) Base Data Rate (Mbps) Clock Divider 2457.6 4915.2 2 3072.0 6144.0 2 4915.2 4915.2 1 6144.0 6144.0 1 11-3 Note: You can use PMA Direct mode in the Transceiver Native PHYs for CPRI applications that require higher frequencies.
11-4 UG-01080 2015.01.19 Deterministic Latency PHY Delay Estimation Logic Figure 11-2: Achieving Deterministic Latency for the TX and RX Datapaths The TX and RX Phase Compensation FIFOs always operate in register mode.
UG-01080 2015.01.19 Deterministic Latency PHY Delay Estimation Logic 11-5 Example 11-1: For RE RX _latency_ RE = + ( + < rx_std_bitslipboundaryselect > delay ) TX_latency_RE = + + Tx bitslip latency > Note: In single width (PMA =10) mode, add one UI delay per value of rx_std_bitslipboundaryselect.
11-6 UG-01080 2015.01.19 Deterministic Latency PHY Delay Estimation Logic Example 11-4: Total Delay Uncertainty Round trip delay estimates are subject to process, voltage, and temperature (PVT) variation.
UG-01080 2015.01.19 11-7 Deterministic Latency PHY Device Family Support PCS Datapath Width RX Phase Comp FIFO Byte Ordering Deserial‐ izer 8B/10B 1.0 1.0 1.0 1.0 16 bits Word Total RX Parallel Aligner (10)(9) Clock Cycles (9)(10) 5.0 9.0 Byte Serializer/Deserializer Turned On 16 bits 1.0 1.0 0.5 or 1.0 0.5 2.0 5.0 or 5.5 32 bits 1.0 1.0 0.5 or 1.0 0.5 2.5 5.5 or 6.0 Table 11-4: PMA Datapath Total Latency The latency numbers in this table are actual hardware delays .
11-8 UG-01080 2015.01.19 Parameterizing the Deterministic Latency PHY Parameterizing the Deterministic Latency PHY This section provides a list of steps on how to configure Deterministic Latency PHY 1. Under Tools > IP Catalog, select the device family of your choice. 2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY, select Deterministic Latency PHY. 3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol. a.
UG-01080 2015.01.19 General Options Parameters for Deterministic Latency PHY Name Value 11-9 Description Data rate Device Dependent If you select a data rate that is not supported by the configuration you have specified, the MegaWizard displays a error message in the message pane. Table 11-7 for sample the channel widths that support these data rates.
11-10 UG-01080 2015.01.19 Additional Options Parameters for Deterministic Latency PHY Channel Width (FPGA-PCS Fabric) Serial Data Rate (Mbps) Single-Width Double-Width 8-Bit 16-Bit 16-Bit 32-Bit 1228.8 Yes Yes Yes Yes 2457.6 No Yes Yes Yes 3072 No Yes Yes Yes 4915.2 No No No Yes 6144 No No No Yes Additional Options Parameters for Deterministic Latency PHY This section describes the settings available on the Additional Options tab for the Deterministic Latency PHY IP core.
UG-01080 2015.01.19 Additional Options Parameters for Deterministic Latency PHY Name Value 11-11 Description Deterministic latency state machine–In this mode, the RX word aligner automatically searches for the word alignment pattern after reset completes. After the word aligner detects the specified word alignment pattern, it sends RX_CLKSLIP to the RX PMA deserial‐ izer indicating the number of bits to slip to compensate for the bits that were slipped to achieve word alignment.
11-12 UG-01080 2015.01.19 Additional Options Parameters for Deterministic Latency PHY Name Value Description Word alignment mode Manual Manual–In this mode, the RX word aligner parses the incoming data stream for a specific alignment character. After it identifies this pattern, it shifts the input stream to align the data and also outputs the number of bits slipped on bitslipboundaryselectout[4:0] for latency compensation on the TX datapath.
UG-01080 2015.01.19 PLL Reconfiguration Parameters for Deterministic Latency PHY Name Enable embedded reset controller Value On/ Off 11-13 Description When you turn this option On, the embedded reset controller handles reset of the TX and RX channels at power up. If you turn this option Off, you must design a reset controller that manages the following reset signals: tx_digitalreset, tx_analogreset, tx_cal_busy, rx_digitalreset, rx_analogreset, and rx_cal_busy.
11-14 UG-01080 2015.01.19 PLL Reconfiguration Parameters for Deterministic Latency PHY Name Value Description Number of reference clocks 1-5 Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index 0-3 Specifies the index for the TX PLL that should be instantiated at startup. Logical index 0 corresponds to TX PLL0, and so on.
UG-01080 2015.01.19 Deterministic Latency PHY Analog Parameters Name Enable channel interface Value On/Off 11-15 Description Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_data and rx_ parallel_data buses increases in the following way: • The rx_parallel_data bus is 64 bits per lane; however, only the low-order number of bits specified by the FPGA fabric transceiver interface width contain valid data.
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UG-01080 2015.01.19 Data Interfaces for Deterministic Latency PHY 11-17 Table 11-9: Avalon-ST TX Interface The following table describes the signals in the Avalon-ST input interface. These signals are driven from the MAC to the PCS. This is an Avalon sink interface. Signal Name Direction Description Input This is TX parallel data driven from the MAC. The ready latency on this interface is 0, so that the PHY must be able to accept data as soon as it comes out of reset.
11-18 UG-01080 2015.01.19 Data Interfaces for Deterministic Latency PHY Table 11-11: Avalon-ST RX Interface The following table describes the signals in the Avalon-ST output interface. These signals are driven from the PCS to the MAC. This is an Avalon source interface. Signal Name Direction Description rx_parallel_data [()-1:0] Output This is RX parallel data driven from the Deterministic Latency PHY IP Core.
UG-01080 2015.01.19 Clock Interface for Deterministic Latency PHY RX Data Word 11-19 Description rx_parallel_data[10] Word Aligner / synchronization status rx_parallel_data[11] Disparity error rx_parallel_data[12] Pattern detect rx_parallel_data[14:13] FIFO status.
11-20 UG-01080 2015.01.19 Optional TX and RX Status Interface for Deterministic Latency PHY Optional TX and RX Status Interface for Deterministic Latency PHY This section describes the optional TX and RX status interface settings for the Deterministic Latency PHY IP core. Table 11-15: Serial Interface and Status Signals Signal Name Direction Signal Name tx_ready Output When asserted, indicates that the TX interface has exited the reset state and is ready to transmit.
UG-01080 2015.01.19 Optional Reset Control and Status Interfaces for Deterministic Latency PHY Signal Name rx_is_lockedtoref [((/) -1:0] rx_is_lockedtodata [(/) -1:0] rx_patterndetect [((/)1:0] rx_rlv [ -1:0] rx_runningdisp [((/)1:0] Direction 11-21 Signal Name Output Asserted when the receiver CDR is locked to the input reference clock. This signal is asynchronous. This signal is optional. Output When asserted, the receiver CDR is in to lock-to-data mode.
11-22 UG-01080 2015.01.19 Register Interface and Descriptions for Deterministic Latency PHY Signal Name rx_cal_busy [-1:0] Direction Output Description When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
UG-01080 2015.01.
11-24 UG-01080 2015.01.19 Register Interface and Descriptions for Deterministic Latency PHY Signal Name Direction Output phy_mgmt_waitrequest Description When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the AvalonMM slave interface must remain constant. Note: Writing to reserved or undefined register addresses may have undefined side effects.
UG-01080 2015.01.19 Register Interface and Descriptions for Deterministic Latency PHY Word Addr Bits [31:0] R/W RW Register Name reset_fine_control 11-25 Description You can use the reset_fine_ control register to create your own reset sequence. In manual mode, only the TX reset occurs automati‐ cally at power on and when the phy_ mgmt_clk_reset is asserted. When pma_rx_setlocktodata or pma_rx_ setlocktodata is set, the transceiver PHY is placed in manual mode.
11-26 UG-01080 2015.01.19 Register Interface and Descriptions for Deterministic Latency PHY Word Addr 0x067 Bits [31:0] R/W RO Register Name pma_rx_is_lockedtoref Description When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n> corresponds to channel < n>. PCS 0x080 [31:0] RW Lane or group number [31:6] R pcs8g_rx_status [5:1] R [0] R Reserved. - [31:1] R pcs8g_tx_status Reserved. [0] RW Reserved - [31:6] RW pcs8g_tx_control Reserved.
UG-01080 2015.01.19 Dynamic Reconfiguration for Deterministic Latency PHY Word Addr 0x085 Bits R/W Register Name [31:4] RW pcs8g_rx_wa_control [3] RW rx_bitslip [2] RW rx_bytereversal_enable [1] RW rx_bitreversal_enable [0] RW rx_enapatternalign 11-27 Description Reserved. Every time this register transitions from 0 to 1, the RX data slips a single bit. To block: Word aligner. When set, enables byte reversal on the RX interface. To block: Byte deserializer RX Phase Comp FIFO.
11-28 UG-01080 2015.01.19 Channel Placement and Utilization for Deterministic Latency PHY Table 11-19: Reconfiguration Interface This table lists the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Signal Name Direction Description reconfig_to_xcvr [(70)-1:0] Input Reconfiguration signals from the Transceiver Reconfiguration Controller. grows linearly with the number of reconfiguration interfaces.
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11-30 UG-01080 2015.01.19 Simulation Files and Example Testbench for Deterministic Latency PHY Related Information SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths. Simulation Files and Example Testbench for Deterministic Latency PHY This section describes simulation file requirements for the Deterministic Latency PHY IP core.
Stratix V Transceiver Native PHY IP Core 12 2015.01.19 UG-01080 Subscribe Send Feedback The Stratix V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike protocol-specific PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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UG-01080 2015.01.19 Performance and Resource Utilization for Stratix V Native PHY 12-3 Performance and Resource Utilization for Stratix V Native PHY This section describes the performance resource utilization for Stratix V native PHY. Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Stratix V Native PHY IP Core uses less than 1% of the available ALMs, memory, primary and secondary logic registers.
12-4 UG-01080 2015.01.19 Parameterizing the Stratix V Native PHY Parameterizing the Stratix V Native PHY This section provides a list of instructions on how to configure the Stratix V Native PHY IP core Complete the following steps to configure the Stratix V Native PHY IP Core 1. 2. 3. 4. Under Tools > IP Catalog, select Stratix V as the device family. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY, select Stratix V Native PHY.
UG-01080 2015.01.19 General Parameters for Stratix V Native PHY Name Number of data channels Bonding mode Range Device Dependent 12-5 Description Specifies the total number of data channels in each direction. From 1-32 channels are supported. Non-bonded or In Non-bonded or x1 mode, each channel is paired with a x1 PLL. If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, ×6/×N merges all the PLLs that meet PLL merging requirements.
12-6 UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY PMA Parameters for Stratix V Native PHY This section describes the PMA parameters for the Stratix V native PHY. Table 12-3: PMA Options The following table describes the options available for the PMA. For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Stratix V Devices. Some parameters have ranges where the value is specified as Device Dependent.
UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY 12-7 TX PMA Parameters Table 12-4: TX PMA Parameters The following table describes the TX PMA options you can specify. For more information about the TX CMU, ATX, and fractional PLLs, refer to the Stratix V PLLs section in Transceiver Architecture in Stratix V Devices.
12-8 UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY Table 12-5: TX PLL Parameters The following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL. Parameter PLL type Range CMU ATX Description You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL.
UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY 12-9 RX CDR Options Table 12-6: RX PMA Parameters The following table describes the RX CDR options you can specify. For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices. Parameter Enable CDR dynamic reconfiguration Range On/Off Description When you turn this option On, you can dynamically change the reference clock input the CDR circuit.
12-10 UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY PMA Optional Ports Table 12-7: RX PMA Parameters The following table describes the optional ports you can include in your IP Core. The QPI interface implements the Intel Quickpath Interconnect. For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices.
UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY Parameter Range 12-11 Description Enable rx_clkslip port On/Off When you turn this option On, the rx_clkslip control input port is enabled. The deserializer slips one clock edge each time this signal is asserted. You can use this feature to minimize uncertainty in the serialization process as required by protocols that require a datapath with deterministic latency such as CPRI.
12-12 UG-01080 2015.01.19 PMA Parameters for Stratix V Native PHY The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports. However, depending upon the interface width selected not all bits on the bus will be active. The following table lists which bits are active for each FPGA Fabric Interface Width selection.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 12-13 Standard PCS Parameters for the Native PHY This section shows the complete datapath and clocking for the Standard PCS and defines the parameters available in the GUI to enable or disable the individual blocks in the Standard PCS.
12-14 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Table 12-11: General and Datapath Parameters The following table describes the general and datapath options for the Standard PCS. Parameter Standard PCS protocol mode Range basic cpri gige srio_2p1 Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 12-15 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The following table describes the options for the phase compensation FIFO.
12-16 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Range Description Enable RX byte ordering On/Off When you turn this option On, the PCS includes the byte ordering block. Byte ordering control mode manual Specifies the control mode for the byte ordering block. The following modes are available: auto • Manual : Allows you to control the byte ordering block • Auto : The word aligner automatically controls the byte ordering block once word alignment is achieved.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Enable rx_std_byteorder_ena port Range On/Off 12-17 Description Enables the optional rx_std_byte_order_ ena control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual. Once byte ordering has occurred, you must deassert and reassert this signal to perform another byte ordering operation.
12-18 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Table 12-14: 8B/10B Encoder and Decoder Parameters Parameter Range Description Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes the 8B/10B encoder. Enable TX 8B/10B disparity control On/Off When you turn this option On, the PCS includes disparity control for the 8B/10B encoder. Your force the disparity of the 8B/ 10B encoder using the tx_forcedisp control signal.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 12-19 When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the following definitions: • Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
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12-22 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter RX word aligner mode Range bit_slip sync_sm manual RX word aligner pattern length 7, 8, 10 16, 20, 32 RX word aligner pattern (hex) 1-256 Number of invalid words to lose sync 1-256 Number of valid data words to decrement error count 1-256 Altera Corporation Specifies one of the following 3 modes for the word aligner: • Bit_slip : You can use bit slip mode to shift the word boundary.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Range Enable rx_std_wa_patternalign port On/Off 12-23 Description Enables the optional rx_std_wa_patternacontrol input port. A rising edge on this signal causes the word aligner to align the next incoming word alignment pattern when the word aligner is configured in manual mode. lign Enable rx_std_wa_a1a2size port On/Off Enables the optional rx_std_wa_a1a2size control input port.
12-24 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Enable rx_std_bitrev_ena port Range On/Off Description When you turn this option On, asserting rx_ std_bitrev_ena control port causes the RX data order to be reversed from the normal order, LSB to MSB, to the opposite, MSB to LSB. This signal is an asynchronous input.
UG-01080 2015.01.19 Standard PCS Pattern Generators 12-25 PRBS Verifier You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns: • Pseudo-random binary sequence (PRBS) • Square wave Table 12-18: PRBS Parameters Parameter Range Enable rx_std_prbs ports Description On/Off When you turn this option On, the PCS includes the rx_std_prbs_done and rx_std_ prbs_err signals to provide status on PRBS operation.
12-26 UG-01080 2015.01.19 Standard PCS Pattern Generators PCS-PMA Width 8-Bit 10-Bit 16-Bit 20-Bit X PRBS-10 PRBS 15 X PRBS 23 X PRBS 31 X X X X X X X X X Unlike the 10G PRBS verifier, the Standard PRBS verifier uses the Standard PCS word aligner. You must specify the word aligner size and pattern. The following table lists the encodings for the available choices.
UG-01080 2015.01.19 Standard PCS Pattern Generators PCS-PMA Width 20-bit PRBS Patterns PRBS Pattern Select Word Aligner Size 12-27 Word Aligner Pattern PRBS 7 3’b000 3’b100 0x0000043040 PRBS 23 3’b001 3’b110 0x00007FFFFF PRBS 15 3’b101 3’b100 0x0000007FFF PRBS 31 3’b110 3’b110 0x007FFFFFFF Registers and Values The following table lists the offsets and registers for the Standard PCS pattern generator and verifier. Note: All undefined register bits are reserved.
12-28 UG-01080 2015.01.19 Standard PCS Pattern Generators Offset OffsetBits R/W 0xA3 [15:0] R/W 0xA4 [15] R/W 0xA6 [5] R/W 0xB8 [13] R/W 0xB9 [11] R/W 0xB A R/W Altera Corporation [11] Name Word Aligner Pattern [15:0] Sync State Machine Disable Auto Byte Align Disable DW Sync State Machine Enable Deterministic Latency State Machine Enable Clock Power Down RX Description Stores the least significant 16 bits from the word aligner pattern as specified in the previous table.
UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY 12-29 10G PCS Parameters for Stratix V Native PHY This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.
12-30 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Table 12-23: General and Datapath Parameters Parameter Range 10G PCS protocol mode basic interlaken sfis teng_baser teng_1588 teng_sdi Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath.
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12-32 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Parameter Range Description Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_ fifo_pfull port. tx_10g_fifo_pfull is synchronous to coreclk. Enable tx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_ fifo_empty port. tx_10g_fifo_empty is pulse-stretched.
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12-34 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Parameter Range Enable RX FIFO control word deletion (Interlaken) On/Off Enable rx_10g_fifo_data_valid port On/Off Description When you turn this option On , the rx_ control_del parameter enables or disables writing the Interlaken control word to RX FIFO. When disabled, a value of 0 for rx_control_del writes all control words to RX FIFO.
UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Parameter Range 12-35 Description Enable rx_10g_fifo_rd_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_rd_en input port. Asserting this signal reads a word from the RX FIFO. This signal is only available for the Interlaken protocol. Enable rx_10g_fifo_align_val port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_ val output port.
12-36 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Parameter Range Description teng_tx_framgen_burst_enable On/Off When you turn this option On, the frame generator burst functionality is enabled. Enable tx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame output port. When asserted, tx_10g_frame indicates the beginning of a new metaframe inside the frame generator.
UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY 12-37 Table 12-27: Interlaken Frame Synchronizer Parameters Parameter Range Description teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled. Enable rx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame output port. This signal is asserted to indicate the beginning of a new metaframe inside.
12-38 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Parameter Range Description Enable rx_10g_frame_diag_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_ err output port. This signal is asserted to indicate a diagnostic control word error. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY 12-39 Table 12-29: 10GBASE-R BER Checker Parameters Parameter Range Description Enable rx_10g_highber port (10GBASE-R) On/Off When you turn this option On, the TX 10G PCS datapath includes the rx_10g_ highber output port. This signal is asserted to indicate a BER of >10 4 . A count of 16 errors in 125- m s period indicates a BER > 10 4 . This signal is only available for the 10GBASE-R protocol.
12-40 UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY Scrambler and Descrambler Parameters TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based on the x58 + x39 +1 polynomial. The scrambler operates in the following two modes: • Synchronous—The Interlaken protocol requires synchronous mode. • Asynchronous (also called self-synchronized)—The 10GBASE-R protocol requires this mode as specified in IEEE 802.3-2008 Clause-49.
UG-01080 2015.01.19 10G PCS Parameters for Stratix V Native PHY 12-41 Block Synchronization The block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a 67-bit word for the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream.
12-42 UG-01080 2015.01.19 10G PCS Pattern Generators Parameter Range Description Enable TX data bitslip On/Off When you turn this option On, the TX gearbox operates in bitslip mode. Enable RX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of RX data allowing you to correct incorrect placement and routing on the PCB. Enable RX data bitslip On/Off When you turn this option On, the 10G PCS RX block synchronizer operates in bitslip mode.
UG-01080 2015.01.19 10G PCS Pattern Generators 12-43 Test Enable bits. The following table lists the offsets and registers of the pattern generators and verifiers in the 10G PCS. Note: The 10G PRBS generator inverts its pattern before transmission. The 10G PRBS verifier inverts the received pattern before verification. You may need to invert the patterns if you connect to thirdparty PRBS pattern generators and checkers. Note: Note: All undefined register bits are reserved.
12-44 UG-01080 2015.01.19 10G PCS Pattern Generators Offset 0x135 Bits R/W Name Description [15:12] R/W Square Wave Pattern Specifies the number of consecutive 1s and 0s. The following values are available: 1, 4, 5, 6, 8, and 10. [10] R/W TX PRBS 7 Enable Enables the PRBS-7 polynomial in the transmitter. [8] R/W TX PRBS 23 Enable Enables the PRBS-23 polynomial in the transmitter. [6] R/W TX PRBS 9 Enable Enables the PRBS-9 polynomial in the transmitter.
UG-01080 2015.01.19 10G PCS Pattern Generators Offset Bits R/W Name 12-45 Description [14] R/W RX PRBS 7 Enable Enables the PRBS-7 polynomial in the receiver. [13] R/W RX PRBS 23 Enable Enables the PRBS-23 polynomial in the receiver. [12] R/W RX PRBS 9 Enable Enables the PRBS-9 polynomial in the receiver. [11] R/W RX PRBS 31 Enable Enables the PRBS-31 polynomial in the receiver. [10] R/W RX Test Enable Enables the PRBS pattern verifier in the receiver.
12-46 UG-01080 2015.01.19 Interfaces for Stratix V Native PHY In addition you have the following options: • You can toggle the Data Pattern Select bit switch between two data patterns. • You can change the value of Seed A and Seed B. Unlike the PRBS pattern generator, the pseudo-random pattern generator does not require a configurable clock. Square Wave Generator To enable the square wave, write the following bits: • • • • Write 1'b1 to the TX Test Enable bit.
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12-48 UG-01080 2015.01.19 Common Interface Ports for Stratix V Native PHY Name Direction Description pll_powerdown[
-1:0] Input When asserted, resets the TX PLL. Active high, edge sensitive reset signal. By default, the Stratix V Native Transceiver PHY IP Cores creates a separate pll_powerdown signal for each logical PLL. However, the Fitter may merge the PLLs if they are in the same transceiver bank. PLLs can only be merged if their pll_powerdown signals are driven from the same source.
UG-01080 2015.01.19 Common Interface Ports for Stratix V Native PHY Name Direction tx_parallel_data[ 64-1:0] Input 12-49 Description PCS TX parallel data. Used when you enable either the Standard or 10G datapath. For the Standard datapath, if you turn on Enable simplified data interface , tx_parallel_ data includes only the data and control signals necessary for the current configura‐ tion. Dynamic reconfiguration of the interface is not supported.
12-50 UG-01080 2015.01.19 Common Interface Ports for Stratix V Native PHY Name Direction Description tx_pma_qpipullup Input Control input port for Quick Path Intercon‐ nect (QPI) applications. When asserted, the transmitted pulls the output signal to high state. Use this port only for QPI applica‐ tions. tx_pma_qpipulldn Input Control input port for Quick Path Intercon‐ nect (QPI) applications. This is an active high signal. When asserted, the transmitter pulls the output signal in low state.
UG-01080 2015.01.19 Common Interface Ports for Stratix V Native PHY Name rx_set_locktoref[ -1:0] Direction Input Description When asserted, programs the RX CDR to manual lock to reference mode in which you control the reset sequence using the rx_ setlocktoref and rx_setlocktodata. Refer to Reset Sequence for CDR in Manual Lock Mode in Transceiver Reset Control in Stratix V Devices for more information about manual control of the reset sequence.
12-52 UG-01080 2015.01.19 Common Interface Ports for Stratix V Native PHY Table 12-39: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding The following table shows the signals within tx_parallel_data that correspond to data, control, and status signals for a single 11-bit word. The tx_parallel_data bus is always 64 bits to enable reconfigurations between the Standard and 10G PCS datapaths. If you only enable the Standard datapath, the 20, high-order bits are not used.
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UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin 12-55 Description rx_std_pcfifo_empty[1:0] Output Yes RX phase compensation FIFO status empty flag. tx_std_pcfifo_full[1:0] Output Yes TX phase compensation FIFO status full flag. tx_std_pcfifo_empty[1:0] Output Yes TX phase compensation FIFO status empty flag. Byte Ordering rx_std_byteorder_ena[1:0] Input No Byte ordering enable.
12-56 UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description rx_std_polinv[-1:0] Input No Polarity inversion for the 8B/10B decoder, When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.
UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin 12-57 Description rx_std_bitslipboundarysel[5-1:0] Output No This signal operates when the word aligner is in bitslip word alignment mode. It reports the number of bits that the RX block slipped to achieve deterministic latency. rx_std_runlength_err[1:0] Output No When asserted, indicates a run length violation.
12-58 UG-01080 2015.01.19 10G PCS Interface Name rx_std_prbs_err Dir Output Synchronous to tx_std_coreclkin/ rx_std_coreclkin Yes Description When asserted, indicates an error only after the rx_std_prbs_done signal has been asserted. This signal pulses for every error that occurs. Errors can only occur once per word.
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12-60 UG-01080 2015.01.19 10G PCS Interface Name tx_10g_clkout [-1:0] rx_10g_clkout [-1:0] rx_10g_clk33out [-1:0] Direction Description Output TX parallel clock output for the TX PCS. Output RX parallel clock output which is recovered from the RX data stream. Output This clock is driven by the RX deserializer. Its frequency is RX CDR PLL clock frequency divided by 33 or equivalently the RX PMA data rate divided by 66.
UG-01080 2015.01.19 10G PCS Interface Name Direction 12-61 Description • [2]: Inversion signal, must always be set to 1'b0.
12-62 UG-01080 2015.01.19 10G PCS Interface Name tx_10g_fifo_pfull [-1:0] tx_10g_fifo_empty [-1:0] tx_10g_fifo_pempty [-1:0] tx_10g_fifo_del [-1:0] tx_10g_fifo_insert [-1:0] Direction Description Output When asserted, indicates that the TX FIFO is partially full. Synchronous to tx_10g_coreclkin. Output TX FIFO empty flag. Synchronous to tx_10g_clkout. This signal is pulse-stretched; you must use a synchron‐ izer. Output TX FIFO partially empty flag.
UG-01080 2015.01.19 10G PCS Interface Name Direction 12-63 Description RX control signals for the Interlaken, 10GBASE-R, and Basic protocols. These are synchronous to rx_10g_coreclkin.
12-64 UG-01080 2015.01.19 10G PCS Interface Name Direction Description Basic mode: 67-bit mode with Block Sync: • [9]: Active-high synchronous status signal that indicates when Block Lock is achieved.
UG-01080 2015.01.19 10G PCS Interface Name rx_10g_fifo_full [-1:0] rx_10g_fifo_pfull [-1:0] rx_10g_fifo_empty [-1:0] rx_10g_fifo_pempty [-1:0] rx_10g_fifo_align_clr [-1:0] rx_10g_fifo_align_en [-1:0] rx_10g_align_val [-1:0] Rx_10g_fifo_del [-1:0] Rx_10g_fifo_insert [-1:0] Direction 12-65 Description Output Active high RX FIFO full flag. Synchronous to rx_10g_ clkout. This signal is pulse-stretched; you must use a synchronizer. Output RX FIFO partially full flag.
12-66 UG-01080 2015.01.19 10G PCS Interface Name tx_10g_diag_status [2-1:0] tx_10g_burst_en [-1:0] tx_10g_frame [-1:0] Direction Description Input For the Interlaken protocol, provides diagnostic status information reflecting the lane status message contained in the Framing Layer Diagnostic Word (bits[33:32]). This message is inserted into the next Diagnostic Word generated by the Frame Generation Block.
UG-01080 2015.01.19 10G PCS Interface Name rx_10g_frame_sync_err [-1:0] Direction Output 12-67 Description For the Interlaken protocol, asserted to indicate a synchronization Control Word error was received in a synchronization Control Word location within the metaframe. This signal is sticky if block lock is lost and does not update until block lock is re-established.This signal is pulse-stretched; you must use a synchronizer to synchronize with rx_10g_clkout.
12-68 UG-01080 2015.01.19 10G PCS Interface Name rx_10g_blk_lock [-1:0] rx_10g_blk_sh_err [-1:0] Direction Description Output Active-high status signal that is asserted when block synchronizer acquires block lock. Valid for the 10GBASE-R and Interlaken protocols, and any basic mode that uses the lock state machine to achieve and monitor block synchronization for word alignment. Once the block synchronizer acquires block lock, it takes at least 16 errors for rx_10g_blk_lock to be deasserted.
UG-01080 2015.01.19 ×6/×N Bonded Clocking Name rx_10g_prbs_err Direction Output 12-69 Description When asserted, indicates an error only after the rx_10g_ prbs_done signal has been asserted. This signal pulses for every error that occurs. An error can only occur once per word. This signal indicates errors for both the PRBS and pseudo-random patterns. Synchronous to rx_10g_ coreclkin. rx_10g_prbs_err_clr Input When asserted, clears the PRBS pattern and de-asserts the rx_10g_prbs_done signal.
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UG-01080 2015.01.19 ×6/×N Bonded Clocking 12-71 Bonded clocks allow you to use the same PLL for up to 13 contiguous channels above and below the TX PLL for a total of 27 bonded channels as the following figure illustrates.
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UG-01080 2015.01.19 xN Non-Bonded Clocking 12-73 You can use the tx_clkout from any channel to transfer data, control, and status signals between the FPGA fabric and the transceiver channels. Using the tx_clkout from the central channel results in overall lower clock skew across lanes. In the FPGA fabric, you can drive the tx_clkout from the connected channel to all other channels in the bonded group.
12-74 UG-01080 2015.01.19 SDC Timing Constraints of Stratix V Native PHY SDC Timing Constraints of Stratix V Native PHY This section describes SDC examples and approaches to identify false timing paths. The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS and 10G PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures.
UG-01080 2015.01.19 Dynamic Reconfiguration for Stratix V Native PHY 12-75 Example 12-2: Using the max_delay Constraint to Identify Asynchronous Inputs You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. The following example illustrates this approach.
12-76 UG-01080 2015.01.19 Simulation Support Example 12-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Device for ×6 or ×N Bonding If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the starting channel number. Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank.
UG-01080 2015.01.19 Slew Rate Settings 12-77 • Protocol declarations take priority over datarate. For example, XAUI has a per-lane datarate of 3.125 Gbps, but only a setting of "3" is allowed. A setting of "4" is not allowed for XAUI. • For protocols not listed in the table, you should use the slew settings associated with your datarate. • The IBIS-AMI slew rate figure is defined as the approximate transmitter 20% - 80% rise time.
Arria V Transceiver Native PHY IP Core 13 2015.01.19 UG-01080 Subscribe Send Feedback The Arria V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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UG-01080 2015.01.19 Performance and Resource Utilization 13-3 Performance and Resource Utilization This section describes performance and resource utilization for the IP core. Because the Standard PCS and PMA are implemented in hard logic, the Arria V Native PHY IP Core requires minimal resources. Parameterizing the Arria V Native PHY By default, the Arria V Native PHY Transceiver PHY IP defaults to the PMA direct datapath and an internal PLL.
13-4 UG-01080 2015.01.19 PMA Parameters Name Range Description Number of data channels 1-36 Specifies the total number of data channels in each direction. Bonding mode Bonded or xN In Non–bonded mode, each channel is assigned a PLL. Non-bonded or x1 If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, merges all the PLLs that meet PLL merging requirements.
UG-01080 2015.01.19 TX PMA Parameters 13-5 Table 13-3: PMA Options Parameter Range Description Data rate Device Dependent Specifies the data rate. The maximum data rate is 12.5 Gbps. PMA direct interface width(12) 8.10,16,20,64,80 Specifies the PMA to FPGA fabric interface width for PMA Direct mode.
13-6 UG-01080 2015.01.19 TX PLL Parameters Table 13-4: TX PMA Parameters Parameter Range Description Enable TX PLL dynamic reconfiguration On/Off When you turn this option On, you can dynamically reconfigure the PLL. This option is also required to simulate TX PLL reconfiguration. If you turn this option On, the Quartus II Fitter prevents PLL merging by default; however, you can specify merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.
UG-01080 2015.01.19 TX PLL Parameters 13-7 Table 13-5: TX PLL Parameters Parameter PLL type PLL base data rate Range CMU Device Dependent Description This is the only PLL type available. Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed from the TX local clock division factor multiplied by the Data rate. Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission.
13-8 UG-01080 2015.01.19 RX PMA Parameters RX PMA Parameters Note: For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the Transceiver Architecture in Arria V Devices . Table 13-6: RX PMA Parameters Parameter Range Description Enable CDR dynamic reconfiguration On/Off When you turn this option On, you can dynamically change the data rate of the CDR circuit. Number of CDR reference clocks 1–5 Specifies the number of reference clocks for the CDRs.
UG-01080 2015.01.19 RX PMA Parameters 13-9 The following table lists the best case latency for the most significant bit of a word for the RX deserializer for the PMA Direct datapath. PMA Direct mode is supported for Arria V GT, ST, and GZ devices only.
13-10 UG-01080 2015.01.19 Standard PCS Parameters FPGA Fabric Interface Width Bus Bits Used 10 bits [9:0] 16 bits {[17:10], [7:0]} 20 bits [19:0] 40 bits [39:0] 64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20], [17:10], [7:0]} 80 bits [79:0] Related Information Transceiver Architecture in Arria V Devices Standard PCS Parameters This section describes the standard PCS parameters. The following figure shows the complete datapath and clocking for the Standard PCS.
UG-01080 2015.01.19 Standard PCS Parameters 13-11 Note: For more information about the Standard PCS, refer to the PCS Architecture section in the Transceiver Architecture in Arria V Devices. The following table describes the general and datapath options for the Standard PCS. Table 13-10: General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY.
13-12 UG-01080 2015.01.19 Phase Compensation FIFO Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the lowspeed parallel clock and FPGA fabric interface clock. Note: For more information refer to the Receiver Phase Compensation FIFO and Transmitter Phase Compensation FIFO sections in the Transceiver Architecture in Arria V Devices.
UG-01080 2015.01.19 Byte Ordering Block Parameters Parameter Range Enable rx_std_rmfifo_ full port 13-13 Description On/Off When you turn this option On, the rate match FIFO outputs a FIFO full status flag. Related Information Transceiver Architecture in Arria V Devices Byte Ordering Block Parameters This section describes the byte ordering block parameters. The RX byte ordering block realigns the data coming from the byte deserializer.
13-14 UG-01080 2015.01.19 Byte Serializer and Deserializer Parameter Range Description Byte order pattern (hex) User-specified 8- Specifies the search pattern for the byte ordering block. 10 bit pattern Byte order pad value (hex) User–specified 8- Specifies the pad pattern that is inserted by the byte ordering 10 bit pattern block. This value is inserted when the byte order pattern is recognized. The byte ordering pattern should occupy the least significant byte (LSB) of the parallel TX data.
UG-01080 2015.01.19 8B/10B 13-15 Table 13-13: Byte Serializer and Deserializer Parameters Parameter Range Description Enable TX byte serializer On/Off When you turn this option On, the PCS includes a TX byte serializer which allows the PCS to run at a lower clock frequency to accommodate a wider range of FPGA interface widths.
13-16 UG-01080 2015.01.19 Rate Match FIFO Table 13-15: Rate Match FIFO Parameters Parameter Range Description Enable RX rate match FIFO On/Off When you turn this option On, the PCS includes a FIFO to compensate for the very small frequency differences between the local system clock and the RX recovered clock. RX rate match insert/ delete +ve pattern (hex) User-specified 20 bit pattern Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.
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UG-01080 2015.01.19 Word Aligner and BitSlip Parameters 13-19 Table 13-17: Word Aligner and BitSlip Parameters Parameter Enable TX bit slip Range On/Off Description When you turn this option On, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the tx_bitslipboundarysel control signal. Enable tx_std_bitslipboundarysel On/Off control input port.
13-20 UG-01080 2015.01.19 Bit Reversal and Polarity Inversion Parameter Range Number of invalid words to lose sync 1–256 Number of valid data words to decrement error count 1–256 Run length detector word count 0–63 Description Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3. Specifies the number of valid data codes that must be received to decrement the error counter.
UG-01080 2015.01.19 Bit Reversal and Polarity Inversion 13-21 Table 13-18: Bit Reversal and Polarity Inversion Parameters Parameter Range Enable TX bit reversal On/Off Enable RX bit reversal On/Off Description When you turn this option On, the word aligner reverses TX parallel data before transmitting it to the PMA for serialization. You can only change this static setting using the Transceiver Reconfiguration Controller.
13-22 UG-01080 2015.01.19 Bit Reversal and Polarity Inversion Parameter Enable tx_std_polinv port Range On/Off Description When you turn this option On, the tx_ std_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. Enable rx_std_polinv port On/Off When you turn this option On, the rx_ std_polinv input is enabled.
UG-01080 2015.01.19 Interfaces 13-23 Interfaces The Native PHY includes several interfaces that are common to all parameterizations. The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.
13-24 UG-01080 2015.01.19 Common Interface Ports Table 13-19: Native PHY Common Interfaces Name Direction Description Clock Inputs and Output Signals tx_pll_refclk[-1:0] Input The reference clock input to the TX PLL. tx_pma_clkout[-1:0] Output TX parallel clock output from PMA. This clock is only available in PMA direct mode. rx_pma_clkout[-1:0] Output RX parallel clock (recovered clock) output from PMA rx_cdr_refclk[-1:0] Input Input reference clock for the RX PFD circuit.
UG-01080 2015.01.19 Common Interface Ports Name tx_analogreset[-1:0] Direction Input 13-25 Description When asserted, resets for TX PMA, TX clock generation block, and serializer. Active high, edge sensitive reset signal. Note: For Arria V devices, while compiling a multi-channel transceiver design, you will see a compile warning (12020) in Quartus II software related to the signal width of tx_analogreset. You can safely ignore this warning.
13-26 UG-01080 2015.01.19 Common Interface Ports Name Direction Description tx_parallel_data[43:0] Input PCS TX parallel data representing 4, 11bit words. Used when you enable the Standard datapath. Refer to Table 13-20for bit definitions. Refer to Table 13-21 various parameterizations. rx_parallel_data[63:0] Output PCS RX parallel data, representing 4, 16bit words. Used when you enable the Standard datapath. Refer to Table 13-22 for bit definitions.
UG-01080 2015.01.19 Common Interface Ports Name Direction 13-27 Description rx_is_lockedtoref[-1:0] Output When asserted, the CDR is locked to the incoming reference clock. rx_clkslip[-1:0] Input When you turn this signal on, the deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment.
13-28 UG-01080 2015.01.19 Common Interface Ports TX Data Word Description tx_parallel_data[9] Force disparity, validates disparity field.
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UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin 13-31 Description rx_std_pcfifo_empty[1:0] Output Yes RX phase compensation FIFO status empty flag. tx_std_pcfifo_full[1:0] Output Yes TX phase compensation FIFO status full flag. tx_std_pcfifo_empty[1:0] Output Yes TX phase compensation FIFO status empty flag. Byte Ordering rx_std_byteorder_ena[1:0] Input No Byte ordering enable.
13-32 UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description rx_std_polinv[-1:0] Input No Polarity inversion for the 8B/10B decoder, When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.
UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin 13-33 Description rx_std_bitslipboundarysel[5-1:0] Output No This signal operates when the word aligner is in bitslip word alignment mode. It reports the number of bits that the RX block slipped to achieve deterministic latency. rx_std_runlength_err[1:0] Output No When asserted, indicates a run length violation.
13-34 UG-01080 2015.01.19 SDC Timing Constraints Name rx_std_prbs_err Dir Output Synchronous to tx_std_coreclkin/ rx_std_coreclkin Yes Description When asserted, indicates an error only after the rx_std_prbs_done signal has been asserted. This signal pulses for every error that occurs. Errors can only occur once per word.
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13-36 UG-01080 2015.01.19 Simulation Support For nonbonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for the Arria V Native PHY with four duplex channels, four TX PLLs, in a nonbonded configuration. For more information about transceiver reconfiguration refer to Transceiver Reconfiguration Controller IP Core.
Arria V GZ Transceiver Native PHY IP Core 14 2015.01.19 UG-01080 Subscribe Send Feedback Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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UG-01080 2015.01.19 Performance and Resource Utilization for Arria V GZ Native PHY 14-3 Performance and Resource Utilization for Arria V GZ Native PHY Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Arria V GZ Native PHY IP Core uses less than 1% of the available ALMs, memory, primary and secondary logic registers. Parameter Presets Presets allow you to specify a group of parameters to implement a particular protocol or application.
14-4 UG-01080 2015.01.19 General Parameters for Arria V GZ Native PHY Clicking Finish generates your customized Arria V GZ Native PHY IP Core. General Parameters for Arria V GZ Native PHY This section describes the datapath parameters in the General Options tab for the Arria V GZ native PHY. Table 14-2: General and Datapath Options The following table lists the parameters available on the General Options tab.
UG-01080 2015.01.19 General Parameters for Arria V GZ Native PHY Name Bonding mode Range Non-bonded or x1 Bonded or ×6/xN fb_compensation 14-5 Description In Non-bonded or x1 mode, each channel is paired with a PLL. If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, merges all the PLLs that meet PLL merging require‐ ments. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances on page 16-57 to observe PLL merging rules.
14-6 UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY PMA Parameters for Arria V GZ Native PHY This section describes the PMA parameters for the Arria V GZ native PHY. Table 14-3: PMA Options The following table describes the options available for the PMA. For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Arria V GZ Devices. Some parameters have ranges where the value is specified as Device Dependent.
UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY 14-7 TX PMA Parameters Table 14-4: TX PMA Parameters The following table describes the TX PMA options you can specify. For more information about the TX CMU, ATX, and fractional PLLs, refer to the Arria V GZ PLLs section in Transceiver Architecture in Arria V GZ Devices.
14-8 UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY TX PLL Table 14-5: TX PLL Parameters The following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL. Parameter PLL type Range CMU ATX Description You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL.
UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY Parameter Selected reference clock source Range 0-4 14-9 Description You can define up to 5 frequencies for the PLLs in your core. The Reference clock frequency selected for index 0 , is assigned to TX PLL<0>. The Reference clock frequency selected for index 1 , is assigned to TX PLL<1>, and so on. RX CDR Options Table 14-6: RX PMA Parameters The following table describes the RX CDR options you can specify.
14-10 UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY Parameter Enable rx_seriallpbken port Range On/Off Description When you turn this option On, the rx_seriallpbken is an input to the core. When your drive a 1 on this input port, the PMA operates in loopback mode with TX data looped back to the RX channel. PMA Optional Ports Table 14-7: RX PMA Parameters The following table describes the optional ports you can include in your IP Core.
UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY Parameter Range 14-11 Description Enable rx_set_lockedtodata and rx_set_locktoref ports On/Off When you turn this option On, the rx_set_lockedtdata and rx_set_lockedtoref ports are outputs of the Enable rx_pma_bitslip_port On/Off When you turn this option On, the rx_pma_bitslip is an input to the core. The deserializer slips one clock edge each time this signal is asserted.
14-12 UG-01080 2015.01.19 PMA Parameters for Arria V GZ Native PHY FPGA Fabric Interface Width Arria V GZ Latency in UI 80 bits 164 The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports. However, depending upon the interface width selected not all bits on the bus will be active.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 14-13 Standard PCS Parameters for the Native PHY This section shows the complete datapath and clocking for the Standard PCS and defines the parameters available in the GUI to enable or disable the individual blocks in the Standard PCS.
14-14 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Table 14-11: General and Datapath Parameters The following table describes the general and datapath options for the Standard PCS. Parameter Standard PCS protocol mode Range basic cpri gige srio_2p1 Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 14-15 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The following table describes the options for the phase compensation FIFO.
14-16 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Range Description Enable RX byte ordering On/Off When you turn this option On, the PCS includes the byte ordering block. Byte ordering control mode manual Specifies the control mode for the byte ordering block. The following modes are available: auto • Manual : Allows you to control the byte ordering block • Auto : The word aligner automatically controls the byte ordering block once word alignment is achieved.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Enable rx_std_byteorder_ena port Range On/Off 14-17 Description Enables the optional rx_std_byte_order_ ena control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual. Once byte ordering has occurred, you must deassert and reassert this signal to perform another byte ordering operation.
14-18 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Table 14-14: 8B/10B Encoder and Decoder Parameters Parameter Range Description Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes the 8B/10B encoder. Enable TX 8B/10B disparity control On/Off When you turn this option On, the PCS includes disparity control for the 8B/10B encoder. Your force the disparity of the 8B/ 10B encoder using the tx_forcedisp control signal.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY 14-19 When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the following definitions: • Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
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14-22 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter RX word aligner mode Range bit_slip sync_sm manual RX word aligner pattern length 7, 8, 10 16, 20, 32 RX word aligner pattern (hex) 1-256 Number of invalid words to lose sync 1-256 Number of valid data words to decrement error count 1-256 Altera Corporation Specifies one of the following 3 modes for the word aligner: • Bit_slip : You can use bit slip mode to shift the word boundary.
UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Range Enable rx_std_wa_patternalign port On/Off 14-23 Description Enables the optional rx_std_wa_patternacontrol input port. A rising edge on this signal causes the word aligner to align the next incoming word alignment pattern when the word aligner is configured in manual mode. lign Enable rx_std_wa_a1a2size port On/Off Enables the optional rx_std_wa_a1a2size control input port.
14-24 UG-01080 2015.01.19 Standard PCS Parameters for the Native PHY Parameter Enable rx_std_bitrev_ena port Range On/Off Description When you turn this option On, asserting rx_ std_bitrev_ena control port causes the RX data order to be reversed from the normal order, LSB to MSB, to the opposite, MSB to LSB. This signal is an asynchronous input.
UG-01080 2015.01.19 Standard PCS Pattern Generators 14-25 PRBS Verifier You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns: • Pseudo-random binary sequence (PRBS) • Square wave Table 14-18: PRBS Parameters Parameter Range Enable rx_std_prbs ports Description On/Off When you turn this option On, the PCS includes the rx_std_prbs_done and rx_std_ prbs_err signals to provide status on PRBS operation.
14-26 UG-01080 2015.01.19 Standard PCS Pattern Generators PCS-PMA Width 8-Bit 10-Bit 16-Bit 20-Bit X PRBS-10 PRBS 15 X PRBS 23 X PRBS 31 X X X X X X X X X Unlike the 10G PRBS verifier, the Standard PRBS verifier uses the Standard PCS word aligner. You must specify the word aligner size and pattern. The following table lists the encodings for the available choices.
UG-01080 2015.01.19 Standard PCS Pattern Generators PCS-PMA Width 20-bit PRBS Patterns PRBS Pattern Select Word Aligner Size 14-27 Word Aligner Pattern PRBS 7 3’b000 3’b100 0x0000043040 PRBS 23 3’b001 3’b110 0x00007FFFFF PRBS 15 3’b101 3’b100 0x0000007FFF PRBS 31 3’b110 3’b110 0x007FFFFFFF Registers and Values The following table lists the offsets and registers for the Standard PCS pattern generator and verifier. Note: All undefined register bits are reserved.
14-28 UG-01080 2015.01.19 Standard PCS Pattern Generators Offset OffsetBits R/W 0xA3 [15:0] R/W 0xA4 [15] R/W 0xA6 [5] R/W 0xB8 [13] R/W 0xB9 [11] R/W 0xB A R/W Altera Corporation [11] Name Word Aligner Pattern [15:0] Sync State Machine Disable Auto Byte Align Disable DW Sync State Machine Enable Deterministic Latency State Machine Enable Clock Power Down RX Description Stores the least significant 16 bits from the word aligner pattern as specified in the previous table.
UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY 14-29 10G PCS Parameters for Arria V GZ Native PHY This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.
14-30 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Table 14-23: General and Datapath Parameters Parameter Range 10G PCS protocol mode Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath.
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14-32 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range Description Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_ fifo_pfull port. tx_10g_fifo_pfull is synchronous to coreclk. Enable tx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_ fifo_empty port. tx_10g_fifo_empty is pulse-stretched.
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14-34 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range Enable RX FIFO alignment word deletion (interlaken) On/Off Enable RX FIFO control word deletion (interlaken) On/Off Enable rx_10g_fifo_data_valid port On/Off Description When you turn this option On, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range 14-35 Description Enable rx_10g_fifo_insert port (10GBASE-R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_insert port. This signal is asserted when a word is inserted into the RX FIFO. This signal is only used for the 10GBASE-R protocol. Enable rx_10g_fifo_rd_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_rd_en input port.
14-36 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Table 14-26: Interlaken Frame Generator Parameters Parameter Range Description teng_tx_framgen_enable On/Off When you turn this option On, the frame generator block of the 10G PCS is enabled. teng_tx_framgen_user_length 0-8192 Specifies the metaframe length. teng_tx_framgen_burst_enable On/Off When you turn this option On, the frame generator burst functionality is enabled.
UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY 14-37 zation process again. Lock status is available to the FPGA fabric. The following table describes the Interlaken frame synchronizer parameters. Table 14-27: Interlaken Frame Synchronizer Parameters Parameter Range Description teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled.
14-38 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range Description Enable rx_10g_frame_skip_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_ err output port. This signal is asserted to indicate the frame synchronization has received an erroneous word in a Skip control word location within the Metaframe. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY 14-39 10GBASE-R BER Checker The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid synchronization headers within a 125-ms period.
14-40 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range Description Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the TX 64b/66b encoder. Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the RX 64b/66b decoder. Scrambler and Descrambler Parameters TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based on the x58 + x39 +1 polynomial.
UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY 14-41 Table 14-32: Interlaken Disparity Generator and Checker Parameters Parameter Range Description Enable Interlaken TX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity generator. This option is available for the Interlaken protocol. Enable Interlaken RX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity checker.
14-42 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Gearbox The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times the PMA width. Table 14-34: Gearbox Parameters Parameter Range Description Enable TX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of TX data allowing you to correct incorrect placement and routing on the PCB.
UG-01080 2015.01.19 10G PCS Pattern Generators 14-43 Table 14-35: PRBS Parameters Parameter Range Enable rx_10g_prbs ports On/Off Description When you turn this option On, the PCS includes the rx_10g_prbs_done , rx_10g_ prbs_err and rx_10g_prbs_err_clrsignals to provide status on PRBS operation. Related Information Transceiver Archictecture in Arria V GZ Devices 10G PCS Pattern Generators The 10G PCS supports the PRBS, pseudo-random pattern, and square wave pattern generators.
14-44 UG-01080 2015.01.19 10G PCS Pattern Generators Offset 0x135 Bits R/W Name Description [15:12] R/W Square Wave Pattern Specifies the number of consecutive 1s and 0s. The following values are available: 1, 4, 5, 6, 8, and 10. [10] R/W TX PRBS 7 Enable Enables the PRBS-7 polynomial in the transmitter. [8] R/W TX PRBS 23 Enable Enables the PRBS-23 polynomial in the transmitter. [6] R/W TX PRBS 9 Enable Enables the PRBS-9 polynomial in the transmitter.
UG-01080 2015.01.19 10G PCS Pattern Generators Offset Bits R/W Name 14-45 Description [14] R/W RX PRBS 7 Enable Enables the PRBS-7 polynomial in the receiver. [13] R/W RX PRBS 23 Enable Enables the PRBS-23 polynomial in the receiver. [12] R/W RX PRBS 9 Enable Enables the PRBS-9 polynomial in the receiver. [11] R/W RX PRBS 31 Enable Enables the PRBS-31 polynomial in the receiver. [10] R/W RX Test Enable Enables the PRBS pattern verifier in the receiver.
14-46 UG-01080 2015.01.19 Interfaces for Arria V GZ Native PHY In addition you have the following options: • You can toggle the Data Pattern Select bit switch between two data patterns. • You can change the value of Seed A and Seed B. Unlike the PRBS pattern generator, the pseudo-random pattern generator does not require a configurable clock. Square Wave Generator To enable the square wave, write the following bits: • • • • Write 1'b1 to the TX Test Enable bit.
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14-48 UG-01080 2015.01.19 Common Interface Ports for Arria V GZ Native PHY Name Direction Description Resets pll_powerdown Input When asserted, resets the TX PLL. Active high, edge sensitive reset signal. By default, the Arria V GZ Native Transceiver PHY IP Core creates a separate pll_powerdown signal for each logical PLL. However, the Fitter may merge the PLLs if they are in the same transceiver bank. PLLs can only be merged if their pll_ powerdown signals are driven from the same source.
UG-01080 2015.01.19 Common Interface Ports for Arria V GZ Native PHY Name tx_parallel_data Direction Input 14-49 Description PCS TX parallel data. Used when you enable either the Standard or 10G datapath. For the Standard datapath, if you turn on Enable simplified data interface , tx_parallel_data includes only the data and control signals necessary for the current configuration. Dynamic reconfiguration of the interface is not supported.
14-50 UG-01080 2015.01.19 Common Interface Ports for Arria V GZ Native PHY Name tx_pma_txdetectrx tx_pma_rxfound rx_pma_qpipulldn Direction Input Output Input Description When asserted, the RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_ pma_txdetectrx request, the receiver detect block initiates the detection process. Only for QPI applications. Indicates the status of an RX detection in the TX PMA. Only for QPI applications.
UG-01080 2015.01.19 Common Interface Ports for Arria V GZ Native PHY Name rx_is_lockedtoref Direction Output [ -1:0] Input rx_clkslip [ -1:0] 14-51 Description When asserted, the CDR is locked to the incoming reference clock. When you turn this signal on, deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment.
14-52 UG-01080 2015.01.19 Common Interface Ports for Arria V GZ Native PHY TX Data Word Description Specifies the current disparity as follows: tx_parallel_data[10] • 1'b0 = positive • 1'b1 = negative Signal Definitions with 8B/10B Disabled TX data bus. is the width specified in the component GUI. tx_parallel_data[-1:0] Unused . is the width specified in the component GUI.
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UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchro‐ nous to tx_ std_ coreclkin/ rx_std_ coreclkin 14-55 Description rx_std_pcfifo_empty[1:0] Output Yes RX phase compensation FIFO status empty flag. tx_std_pcfifo_full[1:0] Output Yes TX phase compensation FIFO status full flag. tx_std_pcfifo_empty[1:0] Output Yes TX phase compensation FIFO status empty flag. Byte Ordering rx_std_byteorder_ena[1:0] Input No Byte ordering enable.
14-56 UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchro‐ nous to tx_ std_ coreclkin/ rx_std_ coreclkin Description rx_std_polinv[-1:0] Input No Polarity inversion for the 8B/10B decoder, When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.
UG-01080 2015.01.19 Standard PCS Interface Ports Name Dir Synchro‐ nous to tx_ std_ coreclkin/ rx_std_ coreclkin 14-57 Description tx_std_bitslipboundarysel[5-1:0] Input No BitSlip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip. rx_std_bitslipboundarysel[5-1:0] Output No This signal operates when the word aligner is in bitslip word alignment mode. It reports the number of bits that the RX block slipped to achieve deterministic latency.
14-58 UG-01080 2015.01.19 10G PCS Interface Name Dir tx_std_elecidle[-1:0] Input rx_std_signaldetect[1:0] Output Synchro‐ nous to tx_ std_ coreclkin/ rx_std_ coreclkin Description When asserted, enables a circuit to detect a downstream receiver. This signal must be driven low when not in use because it causes the TX PMA to enter electrical idle mode with the TX serial data signals in tristate mode. No Signal threshold detect indicator.
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14-60 UG-01080 2015.01.19 10G PCS Interface Name tx_10g_coreclkin [-1:0] rx_10g_coreclkin [-1:0] tx_10g_clkout [-1:0] rx_10g_clkout [-1:0] rx_10g_clk33out [-1:0] Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Description Input — Input — RX parallel clock input that drives the read side of the RX FIFO. Output — TX parallel clock output for the TX PCS. Output — RX parallel clock output which is recovered from the RX data stream.
UG-01080 2015.01.19 10G PCS Interface Name Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin 14-61 Description • [2]: Inversion signal, must always be set to 1'b0.
14-62 UG-01080 2015.01.19 10G PCS Interface Name Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Description When asserted, indicates if tx_data is valid Use of this signal depends upon the protocol you are implementing, as follows: Input Yes Output Yes When asserted, indicates that the TX FIFO is full. Synchronous to tx_std_clkout, Output Yes When asserted, indicates that the TX FIFO is partially full. Output No TX FIFO empty flag. Synchronous to tx_std_ clkout.
UG-01080 2015.01.19 10G PCS Interface Name Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin 14-63 Description RX control signals for the Interlaken, 10GBASE-R, and Basic protocols.
14-64 UG-01080 2015.01.19 10G PCS Interface Name Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Description Basic mode: 67-bit mode with Block Sync: • [9]: Active-high synchronous status signal that indicates when Block Lock is achieved.
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14-66 UG-01080 2015.01.19 10G PCS Interface Name Rx_10g_fifo_insert [-1:0] Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output Yes Description Active-high 10G BaseR RX FIFO insertion flag When asserted, indicates that a word has been inserted into the TX FIFO. This signal is used for the 10GBASE-R protocol. CRC32 rx_10g_crc32err [-1:0] Output No For the Interlaken protocol, asserted to indicate that the CRC32 Checker has found a CRC32 error in the current metaframe.
UG-01080 2015.01.19 10G PCS Interface Name rx_10g_frame_lock [-1:0] Rx_10g_pyld_ins [-1:0] rx_10g_frame_mfrm_err [-1:0] rx_10g_frame_sync_err [-1:0] 14-67 Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Description Output No For the Interlaken protocol, asserted to indicate that the frame synchronizer state machine has achieved frame lock. This signal is pulse-stretched, you must use a synchronizer. This signal is pulse-stretched; you must use a synchronizer.
14-68 UG-01080 2015.01.19 10G PCS Interface Name rx_10g_frame_skip_err [-1:0] Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output No Description For the Interlaken protocol, asserted to indicate a Skip Control Word error was received in a Skip Control Word location within the metaframe. This signal is sticky during the loss of block lock and does not update until block lock is re-established. This signal is pulse-stretched; you must use a synchronizer.
UG-01080 2015.01.19 10G PCS Interface Name Dir Synchro‐ nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin 14-69 Description Bit-Slip Gearbox Feature Synchronizer rx_10g_bitslip [-1:0] tx_10g_bitslip [7-1:0] Input No User control bit-slip in the RX Gearbox. Slips one bit per rising edge pulse. Input No TX bit-slip is controlled by tx_bitslip port. Shifts the number of bit location specified by tx_ bitslip. The maximum shift is .
14-70 UG-01080 2015.01.19 SDC Timing Constraints of Arria V GZ Native PHY SDC Timing Constraints of Arria V GZ Native PHY This section describes SDC examples and approaches to identify false timing paths. The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS and 10G PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures.
UG-01080 2015.01.19 Dynamic Reconfiguration for Arria V GZ Native PHY 14-71 Example 14-2: Using the max_delay Constraint to Identify Asynchronous Inputs You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. The following example illustrates this approach.
14-72 UG-01080 2015.01.19 Simulation Support Example 14-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Arria V GZ Device for ×6 or ×N Bonding If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the starting channel number. Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank.
Cyclone V Transceiver Native PHY IP Core Overview 15 2015.01.19 UG-01080 Subscribe Send Feedback The Cyclone V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Cyclone V Transceiver Native PHY IP Core includes the Standard PCS.
15-2 UG-01080 2015.01.19 Cyclone Device Family Support In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration of the channel and PLLs. You specify the initial configuration when you parameterize the IP core.
UG-01080 2015.01.19 General Parameters 15-3 Note: The Cyclone V Transceiver Native PHY provides presets for CPRI, GIGE, and the Low Latency Standard PCS. The presets specify the parameters required to the protocol specified. General Parameters This section lists the parameters available on the General Options tab. Table 15-2: General and Datapath Options Name Range Device speed grade fastest Description Specifies the speed grade.
15-4 UG-01080 2015.01.19 PMA Parameters Name Bonding mode Range Description Non-bonded or In Non-bonded or x1 mode, each channel is x1 assigned a PLL. Bonded or xN If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, merges all the PLLs that meet PLL merging requirements. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances on page 16-57 to observe PLL merging rules.
UG-01080 2015.01.19 TX PMA Parameters 15-5 Table 15-3: PMA Options Parameter Data rate TX local clock division factor PLL base data rate Range Description Device Dependent Specifies the data rate. The maximum data rate is 12.5 Gbps. 1, 2, 4, 8 Specifies the value of the divider available in the transceiver channels to divide the input clock to generate the correct frequencies for the parallel and serial clocks. This divisor divides the fast clock from the PLL in nonbonded configurations.
15-6 UG-01080 2015.01.19 TX PLL Parameters Parameter Range Description Use external TX PLL On/Off When you turn this option On, the Native PHY does not include TX PLLs. Instead, the Native PHY includes a input clock port for connection to the fast clock from an external PLL, ext_pll_ clk[
-1:0] that you can connect to external PLLs. Use feature when need to perform TX PLL switching between fractional PLL and a CMU PLL.
UG-01080 2015.01.19 RX PMA Parameters Parameter PLL base data rate Range Device Dependent 15-7 Description Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed from the TX local clock division factor multiplied by the Data rate. Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission.
15-8 UG-01080 2015.01.19 RX PMA Parameters Table 15-6: RX PMA Parameters Parameter Enable CDR dynamic reconfigura‐ tion Range On/Off Description When you turn this option On, you can dynamically change the data rate of the CDR circuit. Number of CDR reference clocks 1–5 Specifies the number of reference clocks for the CDRs. Selected CDR reference clock 0–4 Specifies the index of the selected CDR reference clock.
UG-01080 2015.01.19 15-9 Standard PCS Parameters Standard PCS Parameters This section illustrates the complete datapath and clocking for the Standard PCS and defines the parameters available to enable or disable the individual blocks in the Standard PCS.
15-10 UG-01080 2015.01.19 Standard PCS Parameters Table 15-7: General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
UG-01080 2015.01.19 Phase Compensation FIFO Parameter Enable Standard PCS low latency mode Range On/Off 15-11 Description When you turn this option On, all PCS functions are disabled except for the phase compensation FIFO, byte serializer and byte deserializer. This option creates the lowest latency Native PHY that allows dynamic reconfigure between multiple PCS datapaths.
15-12 UG-01080 2015.01.19 Byte Ordering Block Parameters Parameter Range Description Enable rx_std_pcfifo_full port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO full status flag. Enable rx_std_pcfifo_empty port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO empty status flag. Enable rx_std_rmfifo_empty port On/Off When you turn this option On, the rate match FIFO outputs a FIFO empty status flag.
UG-01080 2015.01.19 Byte Ordering Block Parameters Parameter Range 15-13 Description Shows width of the pattern that you must specify. This width depends upon the PCS width and whether or not 8B/10B encoding is used as follows: Byte ordering pattern width 8–10 Width 8B/10B Pad Pattern 8, 16,32 No 8 bits 10,20,40 No 10 bits 8,16,32 Yes 9 bits Byte ordering symbol count 1–2 Byte order pattern (hex) User-specified 8-10 Specifies the search pattern for the byte ordering block.
15-14 UG-01080 2015.01.19 Byte Serializer and Deserializer Related Information Transceiver Architecture in Cyclone V Devices Byte Serializer and Deserializer The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer. This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA interface widths.
UG-01080 2015.01.19 Rate Match FIFO Parameter Range 15-15 Description Enable TX 8B/10B disparity control On/Off When you turn this option On, the PCS includes disparity control for the 8B/10B encoder. You force the disparity of the 8B/10B encoder using the tx_forcedisp and tx_dispval control signal. Enable RX 8B/10B decoder On/Off When you turn this option On, the PCS includes the 8B/10B decoder.
15-16 UG-01080 2015.01.19 Rate Match FIFO Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base Support Solution.
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15-20 UG-01080 2015.01.19 Bit Reversal and Polarity Inversion Parameter Range Description Enable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patternalign control input port. Enable rx_std_wa_a1a2size port On/Off Enables the optional rx_std_wa_a1a2size control input port. Enable rx_std_bitslipboundarysel port On/Off Enables the optional rx_std_wa_bitslipboundarysel status output port.
UG-01080 2015.01.19 Bit Reversal and Polarity Inversion Parameter Enable TX polarity inversion Range On/Off 15-21 Description When you turn this option On, the tx_ std_polinv port controls polarity inversion of TX parallel data before transmitting the parallel data to the PMA. Enable RX polarity inversion On/Off When you turn this option On, asserting rx_std_polinv controls polarity inversion of RX parallel data after PMA transmission.
15-22 UG-01080 2015.01.19 Interfaces Parameter Enable rx_std_signaldetect port Range On/Off Description When you turn this option On, the optional rx_std_signaldetect output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified.
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15-24 UG-01080 2015.01.19 Common Interface Ports Name Direction Description pll_powerdown[
-1:0] Input When asserted, resets the TX PLL. Active high, edge sensitive reset signal. By default, the Cyclone Native Transceiver PHY IP Core create a separate pll_ powerdown signal for each logical PLL. However, the Fitter may merge the PLLs if they are in the same transceiver bank. PLLs can only be merged if their pll_ powerdown signals are driven from the same source.
UG-01080 2015.01.19 Common Interface Ports Name Direction 15-25 Description TX and RX serial ports tx_serial_data[-1:0] Output TX differential serial output data. rx_serial_data[-1:0] Input RX differential serial output data. Control and Status ports rx_seriallpbken[-1:0] Input When asserted, the transceiver enters serial loopback mode. Loopback drives serial TX data to the RX interface.
15-26 UG-01080 2015.01.19 Common Interface Ports Name Direction Input rx_clkslip[-1:0] Description When you turn this signal on, the deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment. As a result, the period of the parallel clock can be extended by 2 unit intervals (UI) during the clock slip operation. This is an optional control input signal.
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15-30 UG-01080 2015.01.19 Cyclone V Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description tx_std_pcfifo_full[1:0] Output Yes TX phase compensation FIFO status full flag. tx_std_pcfifo_empty[1:0] Output Yes TX phase compensation FIFO status empty flag. Byte Ordering rx_std_byteorder_ena[1:0] Input No Byte ordering enable.
UG-01080 2015.01.19 Cyclone V Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin tx_std_polinv[-1:0] Input No 15-31 Description Polarity inversion, part of 8B10B encoder, When set, the TX interface inverts the polarity of the TX data. Rate Match FIFO rx_std_rmfifo_empty[1:0] Output No Rate match FIFO empty flag. When asserted, the rate match FIFO is empty. rx_std_rmfifo_full[1:0] Output No Rate match FIFO full flag.
15-32 UG-01080 2015.01.19 SDC Timing Constraints Name rx_st_wa_patternalign Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Input No Description Active when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_st_wa_patternalign. rx_st_wa_patternalign is edge sensitive. For more information refer to the Word Aligner section in the Transceiver Architec‐ ture in Cyclone V Devices. rx_std_wa_a1a2size[1:0] Input No Used for the SONET protocol.
UG-01080 2015.01.19 Dynamic Reconfiguration 15-33 The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures. You may choose one of the following three approaches to identify these false timing paths to the Quartus II or TimeQuest software. • You can cut these paths in your Synopsys Design Constraints (.
15-34 UG-01080 2015.01.19 Simulation Support For non-bonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for the Cyclone V Native PHY with four duplex channels, four TX PLLs, in a nonbonded configuration. For more information about transceiver reconfiguration refer to Transceiver Reconfiguration Controller IP Core.
Transceiver Reconfiguration Controller IP Core Overview 16 2015.01.19 UG-01080 Subscribe Send Feedback The Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V, Arria V GZ, Cyclone V, and Stratix V devices. Dynamic reconfiguration allows you to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. Dynamic reconfiguration is required for Arria V, Arria V GZ, Cyclone V, and Stratix V devices that include transceivers.
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UG-01080 2015.01.19 Transceiver Reconfiguration Controller System Overview 16-3 Figure 16-1: Transceiver Reconfiguration Controller Altera V-Series FPGA Streaming Data User Application Including MAC Reconfiguration Management Interface to and from Embedded Controller Transceiver Reconfiguration Controller S Transceiver PHY reconfig_from_xcvr[ :0] M reconfig_to_xcvr[ :0] . . Registers to . reconfigure S Master M reconfig_mif_address[31:0] reconfig_mif_read TX and RX Serial Data . . .
16-4 UG-01080 2015.01.19 Transceiver Reconfiguration Controller System Overview The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiver settings: • Register Based—In this access mode you can directly reconfigure a transceiver PHY IP core using the Transceiver Reconfiguration Controller’s reconfiguration management interface.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller Performance and Resource Utilization 16-5 Transceiver Reconfiguration Controller Performance and Resource Utilization This section describes the approximate device resource utilization for a the Transceiver Reconfiguration Controller for Stratix V devices. The numbers of combinational ALUTs and logic registers are rounded to the nearest 50.
16-6 UG-01080 2015.01.19 Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys Complete the following steps to configure the Transceiver Reconfiguration Controller IP Core in Qsys: 1. On the Project Settings tab, select Arria V, Arria V GZ, Cyclone V, or Stratix V from the list. 2. On the Component Library tab, type the following text string in the search box: reconfig.
UG-01080 2015.01.19 General Options Parameters Name Value 16-7 Description Transceiver Calibration Functions Enable offset cancellation On When enabled, the Transceiver Reconfigura‐ tion Controller includes the offset cancellation functionality. This option is always on. Offset cancellation occurs automatically at power-up and runs only once. Enable duty cycle calibration On/Off For Arria V devices, when enable, DCD calibrates for duty cycle distortion caused by clock network skew.
16-8 UG-01080 2015.01.19 Transceiver Reconfiguration Controller Interfaces Name Value Enable PLL reconfiguration support block On/Off Description When enabled, the Transceiver Reconfigura‐ tion Controller includes logic to perform PLL reconfiguration. Transceiver Reconfiguration Controller Interfaces This section describes the top-level signals of the Transceiver Reconfiguration Controller.
UG-01080 2015.01.19 Transceiver Reconfiguration Interface Signal Name Direction 16-9 Description reconfig_mif_read Output When asserted, signals an Avalon-MM read request. reconfig_mif_readdata[15:0] Input The read data. reconfig_mif_waitrequest Input When asserted, indicates that the MIF Avalon-MM slave is not ready to respond to a read request.
16-10 UG-01080 2015.01.19 Reconfiguration Management Interface Signal Name tx_cal_busy Direction Output Description This optional signal is asserted while initial TX calibra‐ tion is in progress and no further reconfiguration operations should be performed. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You can monitor this signal to determine the status of the Transceiver Reconfiguration Controller.
UG-01080 2015.01.19 Reconfiguration Management Interface 16-11 Table 16-7: Reconfiguration Management Interface Signal Name mgmt_clk_clk Direction Input Description Avalon-MM clock input. The frequency range for the mgmt_ clk_clk is 100-125 MHz for Stratix V and Arria V GZ devices. It is 75-125 MHz for Arria V devices. For Cyclone V devices, the frequency range is 75-125MHz if the Cyclone V Hard IP for PCI Express IP Core is not enabled.
16-12 UG-01080 2015.01.19 Transceiver Reconfiguration Controller Memory Map Signal Name Direction Input reconfig_mgmt_read Description Read signal. Active high. Related Information Avalon Interface Specifications Transceiver Reconfiguration Controller Memory Map Each register-based feature has its own Avalon-MM address space within the Transceiver Reconfiguration Controller.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller Calibration Functions 16-13 The following table lists the address range for the Transceiver Reconfiguration Controller and the reconfi‐ guration and signal integrity modules. The Avalon-MM interface uses byte addresses.
16-14 UG-01080 2015.01.19 Auxiliary Transmit (ATX) PLL Calibration Auxiliary Transmit (ATX) PLL Calibration ATX calibration tunes the parameters of the ATX PLL for optimal performance. This function runs once after power up. You can rerun this function by writing into the appropriate memory-mapped registers. The RX buffer is unavailable while this function is running. You should run the ATX calibration after reconfiguring the PLL.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller PMA Analog Control Registers Reconfig Addr Bits [9] R/W Register Name R 16-15 Description Error. When asserted, indicates an error. This bit is asserted if any of the following conditions occur: • The channel address is invalid. • The PHY address is invalid. • The PMA offset is invalid. 7’h0A control and status [8] R Busy. When asserted, indicates that a [1] W Read. Writing a 1 to this bit triggers a read operation. [0] W Write.
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UG-01080 2015.01.19 Transceiver Reconfiguration Controller EyeQ Registers 16-17 EyeQ uses a phase interpolator and sampler to estimate the vertical and horizontal eye opening using the values that you specify for the horizontal phase and vertical height as described in the Table 16-12table. The phase interpolator generates a sampling clock and the sampler examines the data from the sampler output.
16-18 UG-01080 2015.01.19 Transceiver Reconfiguration Controller EyeQ Registers Note: All undefined register bits are reserved. Table 16-12: EyeQ Offsets and Values Note: The default value for all the register bits mentioned in this table is 0. Offset Bits [4:3] R/W RW Register Name BERB Snap Shot and Reset Description Only available when you turn on the Enable Bit Error Rate Block in the Transceiver Reconfigura‐ tion Controller IP Core GUI. The following encodings are defined: • 2'b00: Reserved.
UG-01080 2015.01.19 EyeQ Usage Example Offset 0x3 Bits R/W Register Name 16-19 Description [15:4] RMW Reserved You should not modify these bits. To update this register, first read the value of this register then change only the value for bits that are not reserved. [13] Writing a 1 to this bit selects 1D Eye mode and disables vertical height measurement. Writing a 0 to this bit selects normal 2D Eye measurement mode including both the horizontal and vertical axes.
16-20 UG-01080 2015.01.19 Transceiver Reconfiguration Controller DFE Registers as a diagnostic tool to perform in-system link analysis without interrupting the link traffic. The steps below provide BERB operation example: • • • • Write 3'b111 to bit[2:0] in offset 0x0 to enable BERB Set Horizontal Phase and/or Vertical High in offset 0x1 and/or 0x2 Set 2'b01 to bit[4:3] in offset 0x0 to reset the counters Set 2'b10 to bit [4:3] in offset 0x0 to take a snapshot of the counters.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller DFE Registers Reconfig Addr 7’h1A Bits R/W Register Name 16-21 Description [9] R Error.When asserted, indicates an invalid channel or address. [8] R Busy. When asserted, indicates that a control and status reconfiguration operation is in progress. [1] W Read. Writing a 1 to this bit triggers a read operation. [0] W Write. Writing a 1 to this bit triggers a 7’h1B [5:0] RW 7’h1C [15:0] RW write operation.
16-22 UG-01080 2015.01.19 Controlling DFE Using Register-Based Reconfiguration Offset Bits [3] R/W RW Register Name tap 4 polarity Description Specifies the polarity of the fourth post tap as follows: • 0: negative polarity • 1: positive polarity 0x4 [2:0] RW tap 4 [3] tap 5 polarity RW Specifies the coefficient for the fourth post tap. The valid range is 0–7.
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16-24 UG-01080 2015.01.19 Transceiver Reconfiguration Controller AEQ Registers 1. Read the DFE control and status register busy bit (bit 8) until it is clear. 2. Write the logical channel number of the channel to be updated to the DFE logical channel number register. 3. Write the DFE_offset address of 0x0 (DFE control register). 4. Write the data value 2'b10 to the data register to enable DFE power. This powers up the DFE and DFE adaptation engine is disabled. 5.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller AEQ Registers 16-25 Table 16-15: AEQ Registers Reconfig Addr 7’h28 7’h2A Bits R/W Register Name Description [9:0] RW [9] R Error.When asserted, indicates an error. This bit is asserted when the channel address is invalid. [8] R Busy. When asserted, indicates that a logical channel number control and status The logical channel number of the AEQ hardware to be accessed. Must be specified when performing dynamic updates.
16-26 UG-01080 2015.01.19 Transceiver Reconfiguration Controller ATX PLL Calibration Registers Table 16-16: AEQ Offsets and Values Offset Bits [8] R/W R Register Name adapt_done Description When asserted, indicates that adaptation has completed. In One-Time Adaptation Mode, AEQ stops searching new EQ settings even if the signal quality of incoming serial data is inadequate.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller ATX PLL Calibration Registers 16-27 Table 16-17: ATX Tuning Registers ATX Addr Bits 7’h30 R/W [9:0] RW [9] R 7’h32 Register Name logical channel number Description The logical channel number. The Transceiver Reconfiguration Controller maps the logical address to the physical address. Error. When asserted, indicates an invalid control and status channel or address.
16-28 UG-01080 2015.01.19 Transceiver Reconfiguration Controller PLL Reconfiguration Transceiver Reconfiguration Controller PLL Reconfiguration You can use the PLL reconfiguration registers to change the reference clock input to the TX PLL or the clock data recovery (CDR) circuitry.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller PLL Reconfiguration 16-29 Figure 16-5: Reconfiguration Tab of Native Transceiver PHYs Note: If you dynamically reconfigure PLLs, you must provide your own reset logic by including the Altera Reset Controller IP Core or your own custom reset logic in your design. For more informa‐ tion about the Altera-provided reset controller, refer to Chapter 17, Transceiver PHY Reset Controller IP Core.
16-30 UG-01080 2015.01.19 Transceiver Reconfiguration Controller PLL Reconfiguration Registers Related Information • Transceiver Reset Control in Stratix V Devices • Transceiver Reset Control and Power-Down in Arria V Devices • Transceiver Reset Control and Power Down in Cyclone V Devices Transceiver Reconfiguration Controller PLL Reconfiguration Registers Lists the PLL reconfiguration registers that you can access using Avalon-MM read and write commands on reconfiguration management interface.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller DCD Calibration Registers Reconfig Addr 7’h44 Bits R/W [15:0] RW Register Name 16-31 Description Specifies the read or write data. data Note: All undefined register bits are reserved. Table 16-20: PLL Reconfiguration Offsets and Values Offset 0x0 Bits [2:0] R/W RW Name logical refclk selection Description When written initiates reference clock change to the logical reference clock indexed by bits [2:0].
16-32 UG-01080 2015.01.19 Transceiver Reconfiguration Controller Channel and PLL Reconfiguration DCD runs automatically at power up. After power up, you can rerun DCD by writing to the DCD control register. Altera recommends that you run DCD calibration for Arria V and Cyclone V devices if the data rate is greater than 4.9152 Gbps. Note: All undefined register bits are reserved.
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16-34 UG-01080 2015.01.19 Transceiver Reconfiguration Controller Streamer Module Registers Transceiver Reconfiguration Controller Streamer Module Registers The Streamer module defines the following two modes for channel and PLL reconfiguration: • Mode 0—MIF. Uses a memory initialization file (.mif) to reconfigure settings. • Mode 1—Direct Write. Uses a series of Avalon-MM writes on the reconfiguration management interface to change settings. Note: All undefined register bits are reserved.
UG-01080 2015.01.19 Transceiver Reconfiguration Controller Streamer Module Registers PHY Addr Bits R/W Register Name 16-35 Description [1] W Read. Writing a 1 to this bit triggers a read operation. This bit is self clearing. [0] W Write. Writing a 1 to this bit triggers a write operation. This bit is self clearing. 7’h3B [15:0 RW streamer offset ] When the MIF Mode = 2’b00, the offset register specifies a an internal MIF Streamer register.
16-36 UG-01080 2015.01.19 Mode 0 Streaming a MIF for Reconfiguration Offset Bits [4] R/W RO Register Name MIF or Channel mismatch Description When asserted, indicates the MIF type specified is incorrect. For example, the logical channel is duplex, but the MIF type specifies an RX only channel.
UG-01080 2015.01.19 MIF Generation 16-37 MIF Generation The MIF stores the configuration data for the transceiver PHY IP cores. The Quartus II software automatically generates MIFs after each successful compilation. MIFs are stored in the reconfig_mif folder of the project's working directory. This folder stores all MIFs associated with the compiled project for each transceiver PHY IP core instance in the design. The parameter settings of PHY IP core instance reflect the currently specified MIF.
16-38 UG-01080 2015.01.19 MIF Format The Quartus II software automatically generates MIF for all designs that support POF generation with the following exceptions: • Designs that use bonded channels so that the same TX PLL output drives several channels • GT channels • Non-bonded channels in a design that also includes bonded channels MIF Format The MIF file is organized into records where each record contains the information necessary to carry out the reconfiguration process.
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16-40 UG-01080 2015.01.19 xcvr_diffmifgen Utility information necessary to change from 1 Gbps to 5 Gbps and from 5 Gbps to 1 Gbps. You can use these files to reduce reconfiguration and simulation times. The xcvr_diffmifgen utility can operate on up to five MIF files. This utility only works on MIF files at the same revision level. If you try to compare MIF files that are not at the same revision level, xcvr_diffmifgen issues a warning.
UG-01080 2015.01.19 xcvr_diffmifgen Utility 16-41 Example 16-6: Two Partial MIF files The following example shows and the reduced MIF file, to_MIF_A created by the xcvr_diffmifgen utility: Example 16-7: Reduced MIF File to_MIF_A Note: The xcvr_diffmif utility only works for Quartus II post-fit simulation and hardware.
16-42 UG-01080 2015.01.19 Reduced MIF Creation Reduced MIF Creation The procedure described here is an alternative way to generate a reduced MIF file. You can also use the xcvr_diffmifgen Utility. Follow these steps to generate a reduced MIF: 1. Determine the content differences between the original MIF and the reconfigured MIF. For this example, assume there are bit differences at offset 5 and offset 20. These offsets reside in the PMA-TX and PMA-RX sections of the MIF. 2.
UG-01080 2015.01.19 Register-Based Read 16-43 Example 16-8: Register-Based Write of Logical Channel 0 VOD Setting System Console is used for the following settings: #Setting logical channel 0 write_32 0x8 0x0 #Setting offset to VOD write_32 0xB 0x0 #Setting data register to 40 write_32 0xC 0x28 #Writing all data write_32 0xA 0x1 Ā Register-Based Read Complete the following steps, using a state machine as an example, for a read: 1. 2. 3. 4. 5. 6.
16-44 UG-01080 2015.01.19 Direct Write Reconfiguration Direct Write Reconfiguration Follow these steps to reconfigure a transceiver setting using a series of Avalon-MM direct writes. 1. 2. 3. 4. 5. Write the logical channel number to the Streamer logical channel register. Write Direct Mode, 2'b01, to the Streamer control and status register mode bits. Write the offset address to the Streamer offset register. Write the offset data to the Streamer data register.
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UG-01080 2015.01.19 Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration 16-47 a. Sync badcg, (offset 0xA1, bits[15:14]) b. Enable Comma Detect, (offset 0xA1, bit[13]) c. Enable Polarity, (offset, 0xA1, bit[11]) 8. Now, you must set the proper value for the Sync State Machine Disable bit. • If your PCS/PMA interface width is 8 or 10 bits, perform a read-modify-write with a value of 1'b1 to Sync State Machine Disable (offset 0xA4, bit[15]).
16-48 Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration a. PRBS TX Enable, (0x97, bit[9]) b. PRBS Pattern Select, (0x97, bit[8:6]) UG-01080 2015.01.19 7. Assert the channel reset to begin testing on the new PRBS pattern.
UG-01080 2015.01.
16-50 UG-01080 2015.01.
UG-01080 2015.01.19 Understanding Logical Channel Numbering 16-51 The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TX PLL. Each transceiver PHY IP core reports the number of reconfiguration interfaces it requires in the message pane of its GUI. You must take note of this number so that you can enter it as a parameter in the Transceiver Reconfiguration Controller. The following figure shows the Low Latency PHY IP ore GUI specifying 32 channels.
16-52 UG-01080 2015.01.19 Understanding Logical Channel Numbering Figure 16-10: Transceiver Reconfiguration Controller Interface Bundles The following figure shows a design with two transceiver PHY IP core instances, each with four channels. For this design you would enter 16 for the Number of reconfiguration interfaces and 8, 8 for the Optional interface grouping parameter. Depending upon the transceiver PHY IP core and the parameters specified, the number of reconfigura‐ tion interfaces varies.
UG-01080 2015.01.19 16-53 Two PHY IP Core Instances Each with Four Bonded Channels Two PHY IP Core Instances Each with Four Bonded Channels This section describes logical channel numbering for two transceiver PHY instances, each with four bonded channels, connected to a Transceiver Reconfiguration Controller. When two transceiver PHY instances, each with four bonded channels, are connected to a Transceiver Reconfiguration Controller, the reconfiguration buses of the two instances are concatenated.
16-54 UG-01080 2015.01.19 One PHY IP Core Instance with Eight Bonded Channels Logical Interface Number 12-15 PHY Instance, Interface, or PLL Instance 1, TX PLL. The Fitter assigns all 4 logical TX PLLs to a single physical PLL. One PHY IP Core Instance with Eight Bonded Channels This section describes logical channel numbering for one transceiver instance with eight bonded channels. This example requires the Quartus II Fitter to place channels in two, contiguous transceiver banks.
UG-01080 2015.01.19 Two PHY IP Core Instances Each with Non-Bonded Channels 16-55 Note: Because all of the channels in a transceiver bank share a PLL, this original numbering allows the Fitter to select the optimal CMU PLL from a placement perspective by considering all of the TX PLLs in the bank. The following table shows the channel numbers for post-Fitter and hardware simulations. At this point, you should have assigned channels to pins of the device.
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UG-01080 2015.01.19 Merging TX PLLs In Multiple Transceiver PHY Instances 16-57 Figure 16-12: Correct Connections Stratix V GX, GS, or GT Device Transceiver Reconfiguration Controller to Embedded Processor Reconfig to and from Transceiver Transceiver Bank 3 Transceiver Channels (unused) (unused) 10 GBASE-R S 3 Transceiver Channels Custom CMU PLL Custom The following figure illustrates incorrect connections between two Transceiver Reconfiguration Control‐ lers and six transceiver channels.
16-58 UG-01080 2015.01.19 Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following conditions: • The PLLs connect to the same reset pin. • The PLLs connect to the same reference clock. • The PLLs connect to the same Transceiver Reconfiguration Controller.
UG-01080 2015.01.19 Loopback Modes 16-59 post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. The RX data is also available to the FPGA fabric. In the TX channel, only the TX buffer is active. Figure 16-15: Pre- and Post-CDR Reverse Serial Loopback Paths In this figure, grayed-out blocks are not active in these modes. The number (2) shows the post-CDR loopback path and the number (3) shows pre-CDR reverse serial loopback path.
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Transceiver PHY Reset Controller IP Core 17 2015.01.19 UG-01080 Subscribe Send Feedback The Transceiver PHY Reset Controller IP Core is a highly configurable core that you can use to reset transceivers in Arria V, Arria V GZ, Cyclone V, or Stratix V devices. This reset controller is an alternate controller that you can use instead of the embedded reset controller for the Custom, Low Latency, and Deterministic Latency PHY IP cores.
17-2 UG-01080 2015.01.19 Transceiver PHY Reset Controller IP Core Figure 17-1: Typical System Diagram for the Transceiver PHY Reset Controller IP Core This figure illustrates the typical use of Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the Transceiver Reconfiguration Controller IP Core. You can use the phy_mgmt_clk and phy_mgmt_clk_reset as the clock and reset to the user-controller reset logic.
UG-01080 2015.01.19 Device Family Support for Transceiver PHY Reset Controller 17-3 Related Information • Transceiver Reset Control in Arria V Devices • Transceiver Reset Control in Cyclone V Devices • Transceiver Reset Control in Stratix V Devices Device Family Support for Transceiver PHY Reset Controller This section describes the transceiver PHY reset controller IP core device family support. IP cores provide either final or preliminary support for target Altera device families.
17-4 UG-01080 2015.01.19 Parameterizing the Transceiver PHY Reset Controller IP Parameterizing the Transceiver PHY Reset Controller IP This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Catalog. You can customize the following Transceiver PHY Reset Controller parameters for different modes of operation by clicking Tools > IP Catalog. To parameterize and instantiate the Transceiver PHY Reset Controller IP core: 1.
UG-01080 2015.01.19 Transceiver PHY Reset Controller Parameters Name Range Enable TX PLL reset control On /Off pll_powerdown duration 1-999999999 Synchronize reset input for PLL powerdown 17-5 Description When On, the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL. When Off, the TX PLL reset control is disabled. On /Off Specifies the duration of the PLL powerdown period in ns. The value is rounded up to the nearest clock cycle. The default value is 1000 ns.
17-6 UG-01080 2015.01.19 Transceiver PHY Reset Controller Interfaces Name Range Description RX Channel Enable RX channel reset control On /Off When On, the Transceiver PHY Reset Controller enables the control logic and associated status signals for RX reset. When Off, disables RX reset control and status signals. Use separate RX reset per channel On /Off When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels.
UG-01080 2015.01.19 Transceiver PHY Reset Controller Interfaces 17-7 Figure 17-2: Transceiver PHY Reset Controller IP Core Top-Level Signals Generating the IP core creates signals and ports based on your parameter settings.
17-8 UG-01080 2015.01.19 Transceiver PHY Reset Controller Interfaces Signal Name Direction Clock Domain Description Input Asynchronous This is calibration status signal from the Transceiver PHY IP core. When asserted, the initial calibration is active. When deasserted, calibration has completed. It will not be asserted if you manually re-trigger the calibra‐ tion IP. This signal gates the RX reset sequence. The width of this signals depends on the number of RX channels.
UG-01080 2015.01.19 Transceiver PHY Reset Controller Interfaces Signal Name tx_digitalreset[-1:0] Direction Output Clock Domain Synchronous to the Transceiver PHY Reset Controller input clock. 17-9 Description Digital reset for TX channels. The width of this signal depends on the number of TX channels.
17-10 UG-01080 2015.01.19 Timing Constraints for Bonded PCS and PMA Channels Signal Name rx_digitalreset[ -1:0] Direction Output Clock Domain Synchronous to the Transceiver PHY Reset Controller input clock. Description Digital reset for RX. The width of this signal depends on the number of channels.
UG-01080 2015.01.19 Timing Constraints for Bonded PCS and PMA Channels 17-11 Figure 17-3: Physical Routing Delay Skew in Bonded Channels FPGA Fabric PHY Reset Controller tx_digitalreset TX Channel[ n - 1] TX Channel[1] Bonded TX Channels TX Channel[0] You must provide a Synopsys Design Constraint (SDC) for the reset signals to guarantee that your design meets timing requirements. The Quartus II software generates an .sdc file when you generate the Transceiver Native PHY IP. This .
17-12 Timing Constraints for Bonded PCS and PMA Channels UG-01080 2015.01.19 For more information about the set_max_skew constraint, refer to the SDC and TimeQuest API Reference Manual.
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices 18 2015.01.19 UG-01080 Subscribe Send Feedback When a fractional PLL functions as the TX PLL, you must configure the Native PHY IP Core to use external PLLs. If you also want to use CMU or ATX PLLs, you must use the device-specific Transceiver PLL to instantiate them.
18-2 UG-01080 2015.01.19 Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices Figure 18-1: IP Cores Required for Designs Using the Fractional PLL The following figure show the IP Cores you can instantiate to create designs that use a fractional PLL as the TX PLL. The figure also illustrates the use of Transceiver PLL to instantiate CMU and ATX PLLs. The MegaCore Library includes separate Transceiver PLL and Native PHY IP Cores for each V-Series Device Family.
UG-01080 2015.01.19 Parameterizing the Transceiver PLL PHY 18-3 Parameterizing the Transceiver PLL PHY The IP Catalog provides the following Transceiver PLL IP Cores: Arria V Transceiver, Arria V GZ Transceiver PLL, and Stratix V Transceiver PLL to be used with the Arria V, Arria V GZ and Stratix V Native PHYs, respectively. Complete the following steps to configure a Transceiver PLL IP Core: 1. Under Tools > IP Catalog, select the device familyof your choice. 2.
18-4 UG-01080 2015.01.19 Transceiver PLL Signals Name Value Reference clock frequency Variable Selected reference clock source 0-4 Description Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency. Specifies the index of the TX reference clock for the initial configuration of the TX PLL.
UG-01080 2015.01.
Analog Parameters Set Using QSF Assignments 19 2015.01.19 UG-01080 Subscribe Send Feedback You specify the analog parameters using the Quartus II Assignment Editor, the Pin Planner, or through the Quartus II Settings File (.qsf). The default values for analog options fall into three categories: • Global— These parameters have default values that are independent of other parameter settings. • Computed—These parameters have an initial default value that is recomputed based on other parameter settings.
19-2 UG-01080 2015.01.19 Analog Settings for Arria V Devices a. Double-click in the Assignment Name column and scroll to the bottom of the available assignments. b. Select VCCR_GXB/VCCT_GXB Voltage. c. In the Value column, select 1_0V from the list. The Quartus II software adds these instance assignments commands to the .qsf file for your project.
UG-01080 2015.01.19 XCVR_REFCLK_PIN_TERMINATION 19-3 Assign To Pin - TX & RX serial data XCVR_REFCLK_PIN_TERMINATION Pin Planner and Assignment Editor Name Transceiver Dedicated Refclk Pin Termination Description Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
19-4 UG-01080 2015.01.19 XCVR_VCCR_ VCCT_VOLTAGE XCVR_VCCR_ VCCT_VOLTAGE Pin Planner and Assignment Editor Name VCCR_GXB VCCT_GXB Voltage Description Configures the VCCR_GXB and VCCT_GXB voltage for an GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin. Options 1_1V 1_2V Assign To Pin - TX & RX serial data Analog Settings Having Global or Computed Values for Arria V Devices The following analog parameters have global or computed default values.
UG-01080 2015.01.19 PLL_BANDWIDTH_PRESET 19-5 PLL_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name PLL Bandwidth Preset Description Specifies the PLL bandwidth preset setting Options • • • • Auto Low Medium High Assign To PLL instance XCVR_RX_DC_GAIN Pin Planner and Assignment Editor Name Receiver Buffer DC Gain Control Description Controls the amount of a stage receive-buffer DC gain.
19-6 UG-01080 2015.01.19 XCVR_RX_COMMON_MODE_VOLTAGE XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you also assign a value to this parameter, a Quartus II Fitter error results as shown in the following example: Example 19-1: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value on instance "pci_interface_ddf2:u_pci_interface_2| PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.
UG-01080 2015.01.19 XCVR_RX_LINEAR_EQUALIZER_CONTROL 19-7 XCVR_RX_LINEAR_EQUALIZER_CONTROL Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control Description Static control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0– 2 corresponding to the increasing AC gain.
19-8 UG-01080 2015.01.19 XCVR_RX_SD_ON 1 Assign To Pin - RX serial data XCVR_RX_SD_ON Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal Description Number of parallel cycles to wait before the signal detect block declares presence of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols.
UG-01080 2015.01.19 XCVR_TX_COMMON_MODE_VOLTAGE 19-9 Assign To Pin - RX serial data XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. Note: Contact Altera for using this assignment.
19-10 XCVR_TX_RX_DET_MODE UG-01080 2015.01.19 Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block. Options 0–15 Assign To Pin - TX serial data XCVR_TX_VOD Pin Planner and Assignment Editor Name Transmitter Differential Output Voltage Description Differential output voltage setting.
UG-01080 2015.01.19 Analog Settings for Arria V GZ Devices 19-11 Description When set to DYNAMIC_CTL, the PCS block controls the VOD and pre-emphasis coefficients for PCI Express. When this assignment is set to RAM_CTL the VOD and pre-emphasis are controlled by other assignments, such as XCVR_TX_PRE_EMP_1ST_POST_TAP.
19-12 XCVR_REFCLK_PIN_TERMINATION UG-01080 2015.01.19 Options • • • • • 85_Ohms 100_Ohms 120_Ohms 150_Ohms External_Resistor Assign To Pin - TX & RX serial data XCVR_REFCLK_PIN_TERMINATION Pin Planner and Assignment Editor Name Transceiver Dedicated Refclk Pin Termination Description Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals.
UG-01080 2015.01.19 XCVR_TX_SLEW_RATE_CTRL 19-13 a value to this setting and XCVR_ANALOG_SETTINGS_PROTOCOL results in a Quartus II Fitter error as shown in the following example: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value on instance "pci_interface_ddf2:u_pci_interface_2| PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.U_PCIE_CORE| altpcie_sv_hip_ast_hwtcl:pcie_8x8gb_hardip_2_inst| altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b |sv_xcvr_pipe_native:g_xcvr.
19-14 UG-01080 2015.01.19 XCVR_VCCR_VCCT_VOLTAGE Description Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin. If you do not make this assignment the compiler automatically sets the correct VCCA_GXB voltage depending on the configured data rate, as follows: • Data rate <= 6.5 Gbps: 2_5V • Data rate > 6.5 Gbps: 3_0V.
UG-01080 2015.01.19 master_ch_number 19-15 Description Specifies the CDR bandwidth preset setting Options • • • • Auto Low Medium High Assign To PLL instance master_ch_number Pin Planner and Assignment Editor Name Parameter (Assignment Editor Only) Description For the PHY IP Core for PCI Express (PIPE), specifies the channel number of the channel acting as the master channel for a single transceiver bank or 2 adjacent banks.
19-16 UG-01080 2015.01.19 reserved_channel Options Auto Low Medium High • • • • Assign To PLL instance reserved_channel Pin Planner and Assignment Editor Name Parameter (Assignment Editor Only) Description Allows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express (PIPE), you can use this QSF assignment in conjunction with the master_ch_number assignment to specify channel 4 as the master channel. Available for Gen1, Gen2, and Gen3 variants.
UG-01080 2015.01.19 XCVR_RX_DC_GAIN 19-17 XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you also assign a value to this parameter, a Quartus II Fitter error results as shown in the following example: Example 19-2: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value on instance "pci_interface_ddf2:u_pci_interface_2| PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.
19-18 XCVR_RX_LINEAR_EQUALIZER_CONTROL UG-01080 2015.01.19 Assign To Pin - RX serial data XCVR_RX_LINEAR_EQUALIZER_CONTROL Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control Description Static control for the continuous time equalizer in the receiver buffer. The equalizer has 16 settings from 0–15 corresponding to the increasing AC gain.
UG-01080 2015.01.19 XCVR_RX_SD_ENABLE 19-19 Assign To Pin - RX serial data XCVR_RX_SD_ENABLE Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable/Disable Description Enables or disables the receiver signal detection unit. During normal operation NORMAL_SD_ON=FALSE, otherwise POWER_DOWN_SD=TRUE. Used for the PCIe PIPE PHY, SATA and SAS protocols.
19-20 UG-01080 2015.01.19 XCVR_RX_SD_THRESHOLD Options 0–16 Assign To Pin - RX serial data XCVR_RX_SD_THRESHOLD Pin Planner and Assignment Editor Name Receiver Signal Detection Voltage Threshold Description Specifies signal detection voltage threshold level, Vth. The following encodings are defined: • • • • • • • • SDLV_50MV=7 SDLV_45MV=6 SDLV_40MV=5 SDLV_35MV=4 SDLV_30MV=3 SDLV_25MV=2 SDLV_20MV=1 SDLV_15MV=0 For the PCIe PIPE PHY, SATA, and SAS.
UG-01080 2015.01.19 XCVR_TX_PRE_EMP_PRE_TAP_USER 19-21 XCVR_TX_PRE_EMP_PRE_TAP_USER Pin Planner and Assignment Editor Name Transmitter Pre-emphasis Pre-Tap user Description Specifies the TX pre-emphasis pretap setting value, including inversion. Note: This parameter must be set in conjunction with XCVR_TX_VOD, XCVR_TX_PRE_EMP_1ST_POST_TAP, and XCVR_TX_PRE_EMP_2ND_POST_TAP. All combinations of these settings are not legal. Refer to the Stratix V Device Datasheet for more information.
19-22 XCVR_TX_PRE_EMP_2ND_POST_TAP UG-01080 2015.01.19 Note: This parameter must be set in conjunction with XCVR_TX_VOD, XCVR_TX_PRE_EMP_2ND_POST_TAP, and XCVR_TX_PRE_EMP_PRE_TAP. All combinations of these settings are not legal. Refer to the Arria V GZ Device Datasheet for more information.
UG-01080 2015.01.19 XCVR_TX_PRE_EMP_INV_PRE_TAP 19-23 Assign To Pin - TX serial data Related Information Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment. XCVR_TX_PRE_EMP_INV_PRE_TAP Pin Planner and Assignment Editor Name Transmitter Preemphasis Pre Tap Invert Description Inverts the transmitter pre-emphasis pretap. Specifies the TX pre-emphasis pretap setting value, including inversion.
19-24 UG-01080 2015.01.19 XCVR_TX_RX_DET_ENABLE Related Information Arria V GZ Device Datasheet XCVR_TX_RX_DET_ENABLE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Enable Description Enables or disables the receiver detector circuit at the transmitter. Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block.
UG-01080 2015.01.19 XCVR_TX_VOD 19-25 Assign To Pin - TX serial data XCVR_TX_VOD Pin Planner and Assignment Editor Name Transmitter Differential Output Voltage Description Differential output voltage setting. The values are monotonically increasing with the driver main tap current strength. Note: This parameter must be set in conjunction with XCVR_TX_PRE_EMP_1ST_POST_TAP, XCVR_TX_PRE_EMP_2ND_POST_TAP, and XCVR_TX_PRE_EMP_PRE_TAP. All combinations of these settings are not legal.
19-26 Analog Settings for Cyclone V Devices UG-01080 2015.01.19 Analog Settings for Cyclone V Devices XCVR_IO_PIN_TERMINATION Pin Planner and Assignment Editor Name Transceiver I/O Pin Termination Description Specifies the intended on-chip termination value for the specified transceiver pin. Use External Resistor if you intend to use off-chip termination.
UG-01080 2015.01.19 XCVR_TX_SLEW_RATE_CTRL 19-27 Assign To Pin - PLL refclk pin XCVR_TX_SLEW_RATE_CTRL Pin Planner and Assignment Editor Name Transmitter Slew Rate Control Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with 1 representing the slowest rate.
19-28 CDR_BANDWIDTH_PRESET UG-01080 2015.01.
UG-01080 2015.01.19 XCVR_RX_DC_GAIN 19-29 you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234.
19-30 UG-01080 2015.01.19 XCVR_RX_COMMON_MODE_VOLTAGE Description Static control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0– 2 corresponding to the increasing AC gain. Options 0-2 Assign To Pin - RX serial data XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Receiver Buffer Common Mode Voltage Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment.
UG-01080 2015.01.19 XCVR_RX_SD_ON 19-31 Description Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols. Options 0–29 1 Assign To Pin - RX serial data XCVR_RX_SD_ON Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal Description Number of parallel cycles to wait before the signal detect block declares presence of signal.
19-32 XCVR_TX_COMMON_MODE_VOLTAGE UG-01080 2015.01.19 The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > Vth x 4. For example, a setting of 6 translates to peak-to-peak differential voltage of 180mV (4*45mV). The Vdiff pp must be > 180mV to turn on the signal detect circuit.
UG-01080 2015.01.19 XCVR_TX_RX_DET_ENABLE 19-33 XCVR_TX_RX_DET_ENABLE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Enable Description Enables or disables the receiver detector circuit at the transmitter. Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block.
19-34 UG-01080 2015.01.19 XCVR_TX_VOD_PRE_EMP_CTRL_SRC XCVR_TX_VOD_PRE_EMP_CTRL_SRC Pin Planner and Assignment Editor Name Transmitter VOD Pre-emphasis Control Source Description When set to DYNAMIC_CTL, the PCS block controls the VOD and pre-emphasis coefficients for PCI Express. When this assignment is set to RAM_CTL the VOD and pre-emphasis are controlled by other assignments, such as XCVR_TX_PRE_EMP_1ST_POST_TAP.
UG-01080 2015.01.19 XCVR_IO_PIN_TERMINATION 19-35 Options • 0-15 • 12 (TX) • 9 (RX) Assign To Pin - TX & RX serial data XCVR_IO_PIN_TERMINATION Pin Planner and Assignment Editor Name Transceiver I/O Pin Termination Description Specifies the intended on-chip termination value for the specified transceiver pin. Use External Resistor if you intend to use off-chip termination.
19-36 UG-01080 2015.01.19 XCVR_RX_BYPASS_EQ_STAGES_234 Options • AC_COUPLING • DC_COUPLING_INTERNAL_100_OHMS • DC_COUPLING_EXTERNAL_RESISTOR Assign To Pin - PLL refclk pin XCVR_RX_BYPASS_EQ_STAGES_234 Pin Planner and Assignment Editor Name Receiver Equalizer Stage 2, 3, 4 Bypass Description Bypass continuous time equalizer stages 2, 3, and 4 to save power. This setting eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip short range communication on a PCB.
UG-01080 2015.01.19 XCVR_VCCA_VOLTAGE 19-37 Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with 1 representing the slowest rate. Options 1–5 Assign To Pin - TX serial data XCVR_VCCA_VOLTAGE Pin Planner and Assignment Editor Name VCCA_GXB Voltage Description Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
19-38 Analog Settings Having Global or Computed Default Values for Stratix V Devices UG-01080 2015.01.19 Assign To Pin - TX & RX serial data Related Information Stratix V Device Datasheet Analog Settings Having Global or Computed Default Values for Stratix V Devices The following analog parameters have global or computed default values. You may want to optimize some of these settings. The default value is shown in bold type.
UG-01080 2015.01.19 PLL_BANDWIDTH_PRESET 19-39 Example 19-4: Overriding Default Master Channel Example: set_parameter -name master_ch_number 4 -to ":inst|altera_xcvr_native_sv:testx8_inst| sv_xcvr_native:gen_native_inst.xcvr_native_insts[0]. gen_bonded_group_native.xcvr_native_inst". Options 1, 4 Assign To Include in .qsf file Related Information Transceiver Configurations in Stratix V Devices Refer to Advance [SIC] Channel Placement Guidelines for PIPE Configurations in this document.
19-40 UG-01080 2015.01.19 XCVR_ANALOG_SETTINGS_PROTOCOL Description Allows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express (PIPE), you can use this QSF assignment in conjunction with the master_ch_number assignment to specify channel 4 as the master channel. Available for Gen1, Gen2, and Gen3 variants. Example: set_parameter -name reserved_channel true -to ".
UG-01080 2015.01.19 XCVR_GT_RX_DC_GAIN • • • • • • • • • • • • • • • 19-41 BASIC CEI CPRI INTERLAKEN PCIE_GEN1 PCIE_GEN2 PCIE_GEN3 QPI SFIS SONET SRIO TENG_1588 TENG_BASER TENG_SDI XAUI Assign To Pin - TX and RX serial data XCVR_GT_RX_DC_GAIN Pin Planner and Assignment Editor Name Receiver Buffer DC Gain Control Description Controls the RX buffer DC gain for GTchannels.
19-42 UG-01080 2015.01.19 XCVR_RX_LINEAR_EQUALIZER_CONTROL Assign To Pin - RX serial data XCVR_RX_LINEAR_EQUALIZER_CONTROL Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control Description Static control for the continuous time equalizer in the receiver buffer. The equalizer has 16 settings from 0–15 corresponding to the increasing AC gain.
UG-01080 2015.01.19 XCVR_GT_TX_COMMON_ MODE_VOLTAGE 19-43 XCVR_GT_TX_COMMON_ MODE_VOLTAGE Pin Planner and Assignment Editor Name GT Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. This parameter is only for GT transceivers. Note: Contact Altera for using this assignment.
19-44 UG-01080 2015.01.19 XCVR_GT_TX_PRE_EMP_ PRE_TAP Options • ON • OFF Assign To Pin - TX serial data Related Information Stratix V Device Datasheet XCVR_GT_TX_PRE_EMP_ PRE_TAP Pin Planner and Assignment Editor Name GT Transmitter Preemphasis Pre-Tap Description Specifies the pre-tap pre-emphasis setting. This parameter is only for GT transceivers.
UG-01080 2015.01.19 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 19-45 Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control (PCI Express) Description If enabled equalizer gain control is driven by the PCS block for PCI Express.
19-46 UG-01080 2015.01.19 XCVR_RX_SD_OFF XCVR_RX_SD_OFF Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal Description Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols.
UG-01080 2015.01.19 XCVR_TX_COMMON_MODE_VOLTAGE 19-47 • SDLV_25MV=2 • SDLV_20MV=1 • SDLV_15MV=0 For the PCIe PIPE PHY, SATA, and SAS. The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > Vth x 4. For example, a setting of 6 translates to peak-to-peak differential voltage of 180mV (4*45mV). The Vdiff pp must be > 180mV to turn on the signal detect circuit.
19-48 UG-01080 2015.01.19 XCVR_TX_PRE_EMP_2ND_POST_TAP_USER Related Information • Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment. • Stratix V Device Datasheet XCVR_TX_PRE_EMP_2ND_POST_TAP_USER Pin Planner and Assignment Editor Name Transmitter Preemphasis Second Post-Tap user Description Specifies the transmitter pre-emphasis second post-tap setting value, including inversion.
UG-01080 2015.01.19 XCVR_TX_PRE_EMP_INV_2ND_TAP 19-49 Description Specifies the second post-tap setting value. Note: This parameter must be set in conjunction with XCVR_TX_VOD, XCVR_TX_PRE_EMP_1ST_POST_TAP, and XCVR_TX_PRE_EMP_PRE_TAP. All combinations of these settings are not legal. Refer to the Stratix V Device Datasheet for more information.
19-50 UG-01080 2015.01.19 XCVR_TX_PRE_EMP_PRE_TAP Description Inverts the transmitter pre-emphasis pretap. Specifies the TX pre-emphasis pretap setting value, including inversion. Options • TRUE • FALSE Assign To Pin - TX serial data Related Information Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment.
UG-01080 2015.01.19 XCVR_TX_RX_DET_MODE 19-51 Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block. Options 0–15 Assign To Pin - TX serial data XCVR_TX_RX_DET_OUTPUT_SEL Pin Planner and Assignment Editor Name Transmitter's Receiver Detect Block QPI/PCI Express Control Description Determines QPI or PCI Express mode for the Receiver Detect block.
19-52 UG-01080 2015.01.19 XCVR_TX_VOD_PRE_EMP_CTRL_SRC Description Differential output voltage setting. The values are monotonically increasing with the driver main tap current strength. Note: This parameter must be set in conjunction with XCVR_TX_PRE_EMP_1ST_POST_TAP, XCVR_TX_PRE_EMP_2ND_POST_TAP, and XCVR_TX_PRE_EMP_PRE_TAP. All combinations of these settings are not legal. Refer to the Stratix V Device Datasheet for more information.
Migrating from Stratix IV to Stratix V Devices Overview 20 2013.12.20 UG-01080 Subscribe Send Feedback Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the parameterization process. The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces.
20-2 UG-01080 2013.12.20 Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers Loopback Mode Stratix IV Stratix V Reverse serial loopback (pre- On the Loopback tab of the and post-CDR) ALTGX MegaWizard Plug-In Manager, select either pre-CDR or post-CDR loopback and regenerate the ALTGX IP core. Update the appropriate bits of the Transceiver Reconfiguration Controller tx_rx_word_offset register to enable the pre- or post-CDR reverse serial loopback mode.
UG-01080 2013.12.20 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 20-3 Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP Core to implement dynamic reconfiguration. The ALTGX_RECONFIG IP Core always includes the following two serial buses: • reconfig_from[16:0]— this bus connects to all the channels in a single quad. is the number of quads connected to the ALTGX_RECONFIG IP Core.
20-4 UG-01080 2013.12.20 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments Acceptable PPM threshold between receiver CDR VCO and receiver input reference clock (±1000) Analog power (Auto) Loopback option (No loopback) Enable static equalizer control (Off) DC gain (0) Receiver common mode voltage (0.
UG-01080 2013.12.20 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices 20-5 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
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UG-01080 2013.12.20 Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices 20-7 Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices This section lists the PHY IP Core for PCI Express PHY (PIPE) parameters and the corresponding ALTGX megafunction parameters.
20-8 UG-01080 2013.12.20 Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices ALTGX Parameter Name (Default Value) CI Express PHY (PIPE) Parameter Name Comments Train receiver CDR from pll_inclk (false) TX PLL bandwidth mode (Auto) RX CDR bandwidth mode (Auto) Acceptable PPM threshold (±300) Analog Power(VCCA_L/R) (Auto) Reverse loopback option (No loopback) Enable static equalizer control (false) DC gain (1) RX Vcm (0.
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UG-01080 2013.12.20 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices 20-13 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
20-14 UG-01080 2013.12.20 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices ALTGX(23) rx_freqlocked Custom PHY rx_is_lockedtodata Width [-1:0] Transceiver Control and Status Signals gxb_powerdown phy_mgmt_clk_reset — rx_dataoutfull — — tx_dataoutfull — — There are both pll_locked and rx_pll_clocked in Stratix IV. Stratix V only has pll_ locked.
Additional Information for the Transceiver PHY IP Core 21 2015.01.19 UG-01080 Subscribe Send Feedback This section provides the revision history for the chapters in this user guide. Chapter Document Version Changes Made Getting Started Overview 2.7 Updated the chapter to indicate new IP instantiation flow using the IP Catalog. 10GBASE-R PHY IP Core 2.7 Made the following changes: 10GBASE-KR PHY IP 2.7 Core • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
21-2 UG-01080 2015.01.19 Additional Information for the Transceiver PHY IP Core Chapter Document Version 1G/10Gbps Ethernet PHY IP Core 2.7 XAUI PHY IP Core 2.7 Changes Made Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final for this IP core in Table 5-2: Device Family Support. • Removed erroneous references to 10GBBASE-KR PHY IP Core from this chapter.
UG-01080 2015.01.19 Additional Information for the Transceiver PHY IP Core Chapter Custom PHY IP Core Document Version 2.7 21-3 Changes Made Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final for this IP core in Table 9-1: Device Family Support. • Changed the description of tx_bitslipboundaryselect signal in Optional Status Interfaces section.
21-4 UG-01080 2015.01.19 Additional Information for the Transceiver PHY IP Core Chapter Document Version Stratix V Transceiver Native PHY IP Core 2.7 Arria V Transceiver Native PHY IP Core 2.7 Altera Corporation Changes Made Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support fo final for this IP core in Table 12-1: Device Family Support. • Added a new topic called Slew Rate Settings.
UG-01080 2015.01.19 Additional Information for the Transceiver PHY IP Core Chapter Document Version Arria V GZ Transceiver Native PHY IP Core 2.7 Cyclone V Transceiver Native PHY IP Core 2.7 Changes Made Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final for this IP core in Table 14-1: Device Family Support.
21-6 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version Transceiver PHY Reset Controller IP Core 2.7 Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices 2.7 Changes Made Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final in Table 17-1: Device Family Support.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Backplane Ethernet 10GBASE-KR PHY Document Version 2.6 Changes Made Made the following changes: • Corrected an error in the description of pcs_mode_rc[5:0] in Table 4-17: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC. • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
21-8 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version 1G/10GbE Ethernet PHY IP Core 2.6 XAUI 2.6 Changes Made Made the following changes: • Corrected an error in the description of pcs_mode_rc[5:0] in Table 5-15: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC. • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version Deterministic 2.6 Latency PHY IP Core Changes Made Made the following changes: • Corrected the description of tx_datak signal in Table 11-8: Avalon-ST TX Interface. • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals. Stratix V Transceiver 2.6 Native PHY IP Core Made the following changes: Arria V Transceiver Native PHY IP Core Made the following changes: 2.
21-10 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version Arria V GZ Transceiver Native PHY IP Core 2.6 Cyclone V Transceiver Native PHY IP Core 2.6 Transceiver Reconfi‐ guration Controller IP Core Overview 2.6 Altera Corporation Changes Made Made the following changes: • Removed the description for rx_clklow and rx_fref ports from Table 14-38: Native PHY Common Interfaces.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Analog Parameters Set Using QSF Assignments Chapter Document Version 2.6 21-11 Changes Made Made the following changes: • Corrected values for XCVR_REFCLK_PIN_TERMINATION. DC_ COUPLING_INTERNAL_100_OHM should be DC_COUPLING_ INTERNAL_100_OHMS.
21-12 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version 1G/10GbE Ethernet PHY IP Core 2.5 XAUI 2.5 Changes Made Made the following changes: • Corrected definition of gxmii_rx_d. This signal is synchronous to tx_clkout_1g. • Added frequency for rx_recovered_clk[:0] . It's 257.8 MHz. • Updated the descriptions of rx_latency_adj_1g and tx_ latency_adj_1g. Changed the width of these signals for all references.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version Stratix V Transceiver 2.5 Native PHY IP Core Arria V Transceiver Native PHY IP Core 2.5 Arria V GZ Transceiver Native PHY IP Core 2.5 Cyclone V Transceiver Native PHY IP Core 2.5 Changes Made Made the following changes: • Corrected Figure 12-4 showing the 10G PCS datapath. This datapath does not include hard IP blocks to implement KR-FEC.
21-14 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Chapter Document Version Transceiver Reconfi‐ guration Controller IP Core Overview 2.5 Transceiver Reset Controller IP Core Overview 2.5 Analog Parameters Set Using QSF Assignments 2.5 Altera Corporation Changes Made Made the following changes: • Updated table for "Device Support for Dynamic Reconfigura‐ tion" to indicate that Arria® V and Cyclone ® V devices support TX PLL switching.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 1G/10Gbps Ethernet PHY IP Core 2.4 Backplane Ethernet 10GBASE-KR PHY IP Core 2.4 21-15 Changes Made Added descriptions of FEC-related bits: C2[8], CB[26:25]. PHY IP Core for PCI 2.4 Express (PIPE) Date Document Version Changes Made 1G/10Gbps Ethernet PHY IP Core 2.3 Changed speed of rx_recovered_clk from 125 MHz or 156.25 MHz to 125 MHz or 257.8125 MHz .
21-16 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version Changes Made Introduction April 2013 2.1 Update to introduction. Renamed heading "Additional Transceiver PHYs" to "Non-Protocol-Specific Transceiver PHYs." 2.1 No changes from previous release. 2.1 No changes from previous release. 2.1 No changes from previous release. 2.1 No changes from previous release. 2.1 Fixed minor topographical error in heading. 2.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 21-17 Changes Made Transceiver Reconfiguration Controller April 2013 2.1 Rename table 16-13 to DFE Registers. Fix typo in Reconfig Addr column changed 7’h11 to 7’h19. In Table 16-8, removed the DCD Calibration registers row. Transceiver Reset Controller April 2013 2.1 No changes from previous release. Transceiver Reset Controller April 2013 2.1 No changes from previous release.
21-18 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version March 2013 2.0 Changes Made Made the following changes: • Improved the description of automatic speed detection. • Updated speed grade information. • Updated definition of KR AN Link Ready[5:0] to include 1000BASE-KX. • Added the following registers SEQ LT timeout at 0xB1, Bit 2 and SEQ Reconfig Mode[5:0] 0xB1, Bits[13:8] registers • Revised Functional Description section.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 21-19 Changes Made Stratix V Native PHY March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL. Arria V Native PHY March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL. Arria V GZ Native PHY March 2013 2.
21-20 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version March 2013 2.0 Changes Made Initial Release. Analog Parameters Set Using QSF Assignment March 2013 2.0 Made the following changes. • Changed choices for XCVR_RX_SD_ENABLE from TRUE/FALSE to On/Off • Corrected definitions of XCVR_IO_PIN_TERMINATION and XCVR_ GT_IO_PIN_TERMINATION which were reversed.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date February 2013 Document Version 1.9 21-21 Changes Made • Reformatted. • Corrected definition of rx_data_ready. This signal is used and indicates that the PCS is ready to receive data. • Removed description of PMA reset_ch_bitmask at 0x41 and reset_control at 0x42 which are not available. • Removed definitions of trn_in_trigger and trn_out_ trigger buses which are not used. XAUI PHY February 2013 1.
21-22 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date February 2013 Document Version 1.9 Changes Made • Reformatted. • Removed QPI signals from Figure showing Arria V Native PHY Common Interfaces. These signals are not available for Arria V devices. • Removed SDC constraints for 10G signals which are not available for Arria V. Arria V GZ Native PHY February 2013 1.9 • Reformatted. • Improved definition of pll_powerdown signal.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version November 2012 1.8 21-23 Changes Made • Expanded discussion of the Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Native PHY IP Cores. • Added Riviera-PRO Aldec simulation directory. 10GBASE-R PHY November 2012 1.8 • Added support for IEEE 1588 Precision Time Protocol. • Added Arria V GZ support.
21-24 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version November 2012 1.8 Changes Made • • • • • • • • • • Added Gen3 support. Added Arria V GZ support. Added ×2 support. Added discussion of link equalization for Gen3. Added timing diagram showing rate change to Gen3. Revised presentation of signals. Corrected the definition of rx_eidleinfersel[3-1:0]. Moved Analog Options to a separate chapter.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 21-25 Changes Made Arria V Transceiver Native PHY November 2012 1.8 • • • • Added support for Standard datapath. Added support for multiple PLLs. Moved Analog Options to a separate chapter. Added constraint for tx_digitalreset when TX PCS uses bonded clocks. Arria V GZ Transceiver Native PHY November 2012 1.8 • Initial release. Cyclone V Transceiver Native PHY November 2012 1.
21-26 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version November 2012 1.8 Changes Made • Created separate chapter for analog parameters that were previously listed in the individual transceiver PHY chapters. • Changed default value for XCVR_GT_RX_COMMON_MODE_VOLTAGE to 0.65V. Introduction and Getting Started June 2012 1.7 • Added brief discussion of the Stratix V and Arria V Transceiver Native PHY IP Cores.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version June 2012 1.7 21-27 Changes Made • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_ USER, and 11 new settings for GT transceivers. • Added reference Transceiver device handbook chapters for detailed explanation of PCS blocks.
21-28 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version Changes Made PHY IP Core for PCI Express (PIPE) June 2012 1.7 • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_ USER, and 11 new settings for GT transceivers. • Added reference Stratix V Transceiver Architecture chapter for detailed explanation of PCS blocks.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version June 2012 1.7 21-29 Changes Made • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_ USER, and 11 new settings for GT transceivers. • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
21-30 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version June 2012 1.7 Changes Made • DFE now automatically runs offset calibration and phase interpolator (PI) phase calibration at power on. • Added section explaining how to generate a reduced MIF file. • Corrected definition of EyeQ control register. Writing a 1 to bit 0 enables the Eye monitor. • Corrected bit-width typos in PMA Analog Registers.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 21-31 Changes Made Low Latency PHY February 2012 1.5 • Added register definitions for Low Latency PHY. Deterministic Latency PHY February 2012 1.5 • Removed pma_rx_signaldetect register. The Deterministic Latency PHY does not support this functionality.
21-32 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version December 2011 1.4 Changes Made • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive. Custom December 2011 1.4 • Added ×N and feedback compensation options for bonded clocks. • Added Enable Channel Interface parameter which is required for dynamic reconfiguration of transceivers.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version December 2011 1.4 21-33 Changes Made • Added duty cycle distortion (DCD) signal integrity feature. • Added PLL and channel reconfiguration using a memory initial‐ ization file (.mif). • Added ability to reconfigure PLLs, including the input reference clock or to change the PLL that supplies the high speed serial clock to the serializer without including logic to reconfigure channels.
21-34 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version Changes Made Interlaken Transceiver PHY November 2011 1.3 • Added tx_sync_done signal which indicates that all lanes of TX data are synchronized. • tx_coreclk_in is required in this release. • Added base data rate, lane rate, input clock frequency, and PLL type parameters.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version November 2011 1.3 21-35 Changes Made • Added MIF support to allow transceiver reconfiguration from a .mif file that may contain updates to multiple settings. • Added support for the following features: • EyeQ • AEQ • ATX tuning • PLL reconfiguration • DC gain and four-stage linear equalization for the RX channels • Removed Stratix IV device support.
21-36 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version May 2011 1.2 Changes Made • Added simulation section. • Revised Figure 1–1 on page 1–1 to show the Transceiver Reconfiguration Controller as a separately instantiated IP core. • Added statement saying that the transceiver PHY IP cores do not support the NativeLink feature of the Quartus II software. • Revised reset section. Getting Started May 2011 1.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version May 2011 1.2 21-37 Changes Made • Added details about the 0 ready latency for tx_ready. • Added PLL support to lane rate parameter description in Interlaken PHY General Options. • Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
21-38 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version May 2011 1.2 Changes Made • Added presets for the 2.50 GIGE and 1.25GIGE protocols. • Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core. • Removed device support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version 21-39 Changes Made Migrating from Stratix IV to Stratix V May 2011 1.2 • Added discussion of dynamic reconfiguration for Stratix IV and Stratix V devices. • Added information on loopback modes for Stratix IV and Stratix V devices. • Added new parameters for Custom PHY IP Core in Stratix V devices. All Chapters December 2010 1.
21-40 UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version December 2010 1.1 Changes Made • • • • • Added Stratix V support Changed phy_mgmt_address from 16 to 9 bits. Renamed management interface, adding phy_ prefix Renamed block_lock and hi_ber signals rx_block_lock and rx_hi_ber, respectively. • Added top-level signals for external PMA and reconfigura‐ tion controller in Stratix IV devices.
UG-01080 2015.01.19 Revision History for Previous Releases of the Transceiver PHY IP Core Date Document Version December 2010 1.1 21-41 Changes Made • • • • Added simulation support in ModelSim SE Added PIPE low latency configuration option Changed phy_mgmt_address from 16 to 9 bits. Changed register map to show word addresses instead of a byte offset from a base address.
21-42 UG-01080 2015.01.19 How to Contact Altera Date Document Version Changes Made November 2010 1.1 • Corrected address offsets in PMA Analog Registers. These are byte offsets and should be: 0x00, 0x04, 0x08, 0x0C, 0x10, not 0x00, 0x01, 0x02, 0x03, 0x04. • Corrected base address for transceiver reconfiguration control and status registers in PMA Analog Registers. It should be 0x420, not 0x400. • Corrected byte offsets in Custom PHY IP Core Registers and PCI Express PHY (PIPE) IP Core Registers.
