User guide

ManualsBrandsAltera ManualsConsumer electronicsUG-01080

171

172

173

174

175

176

177

178

179

180

Table Of Contents

Altera Transceiver PHY IP Core User Guide
Contents
1. Introduction to the Protocol-Specific and Native Transceiver PHYs
- Protocol-Specific Transceiver PHYs
- Native Transceiver PHYs
- Non-Protocol-Specific Transceiver PHYs
- Transceiver PHY Modules
- Transceiver Reconfiguration Controller
- Resetting the Transceiver PHY
- Running a Simulation Testbench
- Unsupported Features
2. Getting Started Overview
- Installation and Licensing of IP Cores
- Design Flows
- MegaWizard Plug-In Manager Flow
  - Specifying Parameters
  - Simulate the IP Core
3. 10GBASE-R PHY IP Core
- 10GBASE-R PHY Release Information
- 10GBASE-R PHY Device Family Support
- 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices
- 10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices
- 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
- Parameterizing the 10GBASE-R PHY
- General Option Parameters
- Analog Parameters for Stratix IV Devices
- 10GBASE-R PHY Interfaces
- 10GBASE-R PHY Data Interfaces
- 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces
- Optional Reset Control and Status Interface
- 10GBASE-R PHY Clocks for Arria V GT Devices
- 10GBASE-R PHY Clocks for Arria V GZ Devices
- 10GBASE-R PHY Clocks for Stratix IV Devices
- 10GBASE-R PHY Clocks for Stratix V Devices
- 10GBASE-R PHY Register Interface and Register Descriptions
- 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices
- 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices
- 1588 Delay Requirements
- 10GBASE-R PHY TimeQuest Timing Constraints
- 10GBASE-R PHY Simulation Files and Example Testbench
4. Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
- 10GBASE-KR PHY Release Information
- Device Family Support
- 10GBASE-KR PHY Performance and Resource Utilization
- Parameterizing the 10GBASE-KR PHY
- 10GBASE-KR PHY IP Core Functional Description
- 10GBASE-KR PHY Arbitration Logic Requirements
- 10GBASE-KR PHY State Machine Logic Requirements
- Forward Error Correction (Clause 74)
- 10BASE-KR PHY Interfaces
- 10GBASE-KR PHY Clock and Reset Interfaces
- Register Interface Signals
- 10GBASE-KR PHY Register Definitions
- PMA Registers
- PCS Registers
- Creating a 10GBASE-KR Design
- Editing a 10GBASE-KR MIF File
- Design Example
- SDC Timing Constraints
- Acronyms
5. 1G/10 Gbps Ethernet PHY IP Core
- 1G/10GbE PHY Release Information
- Device Family Support
- 1G/10 GbE PHY Performance and Resource Utilization
- Parameterizing the 1G/10GbE PHY
- 1GbE Parameters
- Speed Detection Parameters
- PHY Analog Parameters
- 1G/10GbE PHY Interfaces
- 1G/10GbE PHY Clock and Reset Interfaces
- 1G/10GbE PHY Data Interfaces
- XGMII Mapping to Standard SDR XGMII Data
- Serial Data Interface
- 1G/10GbE Control and Status Interfaces
- Register Interface Signals
- 1G/10GbE PHY Register Definitions
- PMA Registers
- PCS Registers
- 1G/10 GbE GMII PCS Registers
- PMA Registers
- 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE
- 1G/10GbE PHY Arbitration Logic Requirements
- 1G/10GbE PHY State Machine Logic Requirements
- Editing a 1G/10GbE MIF File
- Creating a 1G/10GbE Design
- Dynamic Reconfiguration Interface Signals
- 1G/10 Gbps Ethernet PHY IP Core
- Design Example
- Simulation Support
- TimeQuest Timing Constraints
- Acronyms
6. XAUI PHY IP Core
- XAUI PHY Release Information
- XAUI PHY Device Family Support
- XAUI PHY Performance and Resource Utilization for Stratix IV Devices
- XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
- Parameterizing the XAUI PHY
- XAUI PHY General Parameters
- XAUI PHY Analog Parameters
- XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices
- Advanced Options Parameters
- XAUI PHY Configurations
- XAUI PHY Ports
- XAUI PHY Data Interfaces
  - SDR XGMII TX Interface
  - SDR XGMII RX Interface
  - Transceiver Serial Data Interface
- XAUI PHY Clocks, Reset, and Powerdown Interfaces
- XAUI PHY PMA Channel Controller Interface
- XAUI PHY Optional PMA Control and Status Interface
- XAUI PHY Register Interface and Register Descriptions
- XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
- XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices
  - Logical Lane Assignment Restriction
  - XAUI PHY Dynamic Reconfiguration Interface Signals
- SDC Timing Constraints
- Simulation Files and Example Testbench
7. Interlaken PHY IP Core
- Interlaken PHY Device Family Support
- Parameterizing the Interlaken PHY
- Interlaken PHY General Parameters
- Interlaken PHY Optional Port Parameters
- Interlaken PHY Analog Parameters
- Interlaken PHY Interfaces
- Interlaken PHY Avalon-ST TX Interface
- Interlaken PHY Avalon-ST RX Interface
- Interlaken PHY TX and RX Serial Interface
- Interlaken PHY PLL Interface
- Interlaken Optional Clocks for Deskew
- Interlaken PHY Register Interface and Register Descriptions
- Why Transceiver Dynamic Reconfiguration
- Dynamic Transceiver Reconfiguration Interface
- Interlaken PHY TimeQuest Timing Constraints
- Interlaken PHY Simulation Files and Example Testbench
8. PHY IP Core for PCI Express (PIPE)
- PHY for PCIe (PIPE) Device Family Support
- PHY for PCIe (PIPE) Resource Utilization
- Parameterizing the PHY IP Core for PCI Express (PIPE)
- PHY for PCIe (PIPE) General Options Parameters
- PHY for PCIe (PIPE) Interfaces
- PHY for PCIe (PIPE) Input Data from the PHY MAC
- PHY for PCIe (PIPE) Output Data to the PHY MAC
- PHY for PCIe (PIPE) Clocks
- PHY for PCIe (PIPE) Clock SDC Timing Constraints for Gen3 Designs
- PHY for PCIe (PIPE) Optional Status Interface
- PHY for PCIe (PIPE) Serial Data Interface
- PHY for PCIe (PIPE) Register Interface and Register Descriptions
- PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate
- Enabling Dynamic PMA Tuning for PCIe Gen3
- PHY for PCIe (PIPE) Dynamic Reconfiguration
  - Logical Lane Assignment Restriction
- PHY for PCIe (PIPE) Simulation Files and Example Testbench
9. Custom PHY IP Core
- Device Family Support
- Performance and Resource Utilization
- Parameterizing the Custom PHY
- Interfaces
10. Low Latency PHY IP Core
- Device Family Support
- Performance and Resource Utilization
- Parameterizing the Low Latency PHY
- General Options Parameters
- Additional Options Parameters
- PLL Reconfiguration Parameters
- Low Latency PHY Analog Parameters
- Low Latency PHY Interfaces
- Low Latency PHY Data Interfaces
- Optional Status Interface
- Low Latency PHY Clock Interface
- Optional Reset Control and Status Interface
- Register Interface and Register Descriptions
- Dynamic Reconfiguration
- SDC Timing Constraints
- Simulation Files and Example Testbench
11. Deterministic Latency PHY IP Core
- Deterministic Latency Auto-Negotiation
- Achieving Deterministic Latency
- Deterministic Latency PHY Delay Estimation Logic
- Deterministic Latency PHY Device Family Support
- Parameterizing the Deterministic Latency PHY
- Interfaces for Deterministic Latency PHY
- Data Interfaces for Deterministic Latency PHY
- Clock Interface for Deterministic Latency PHY
- Optional TX and RX Status Interface for Deterministic Latency PHY
- Optional Reset Control and Status Interfaces for Deterministic Latency PHY
- Register Interface and Descriptions for Deterministic Latency PHY
- Dynamic Reconfiguration for Deterministic Latency PHY
- Channel Placement and Utilization for Deterministic Latency PHY
- SDC Timing Constraints
- Simulation Files and Example Testbench for Deterministic Latency PHY
12. Stratix V Transceiver Native PHY IP Core
- Device Family Support for Stratix V Native PHY
- Performance and Resource Utilization for Stratix V Native PHY
- Parameter Presets
- Parameterizing the Stratix V Native PHY
- Interfaces for Stratix V Native PHY
- ×6/×N Bonded Clocking
- xN Non-Bonded Clocking
- SDC Timing Constraints of Stratix V Native PHY
- Dynamic Reconfiguration for Stratix V Native PHY
- Simulation Support
- Slew Rate Settings
13. Arria V Transceiver Native PHY IP Core
- Device Family Support
- Performance and Resource Utilization
- Parameterizing the Arria V Native PHY
- General Parameters
- PMA Parameters
- Standard PCS Parameters
- Interfaces
  - Common Interface Ports
  - Standard PCS Interface Ports
- SDC Timing Constraints
- Dynamic Reconfiguration
- Simulation Support
14. Arria V GZ Transceiver Native PHY IP Core
- Device Family Support for Arria V GZ Native PHY
- Performance and Resource Utilization for Arria V GZ Native PHY
- Parameter Presets
- Parameterizing the Arria V GZ Native PHY
- Interfaces for Arria V GZ Native PHY
- SDC Timing Constraints of Arria V GZ Native PHY
- Dynamic Reconfiguration for Arria V GZ Native PHY
- Simulation Support
15. Cyclone V Transceiver Native PHY IP Core Overview
- Cyclone Device Family Support
- Cyclone V Native PHY Performance and Resource Utilization
- Parameterizing the Cyclone V Native PHY
- General Parameters
- PMA Parameters
- Standard PCS Parameters
- Interfaces
  - Common Interface Ports
  - Cyclone V Standard PCS Interface Ports
- SDC Timing Constraints
- Dynamic Reconfiguration
- Simulation Support
16. Transceiver Reconfiguration Controller IP Core Overview
- Transceiver Reconfiguration Controller System Overview
- Transceiver Reconfiguration Controller Performance and Resource Utilization
- Parameterizing the Transceiver Reconfiguration Controller IP Core
- Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys
  - General Options Parameters
- Transceiver Reconfiguration Controller Interfaces
  - MIF Reconfiguration Management Avalon-MM Master Interface
  - Transceiver Reconfiguration Interface
  - Reconfiguration Management Interface
- Transceiver Reconfiguration Controller Memory Map
- Transceiver Reconfiguration Controller Calibration Functions
  - Offset Cancellation
  - Duty Cycle Calibration
  - Auxiliary Transmit (ATX) PLL Calibration
- Transceiver Reconfiguration Controller PMA Analog Control Registers
- Transceiver Reconfiguration Controller EyeQ Registers
  - EyeQ Usage Example
- Transceiver Reconfiguration Controller DFE Registers
- Controlling DFE Using Register-Based Reconfiguration
  - Turning on DFE Continuous Adaptive mode
  - Turning on Triggered DFE Mode
  - Setting the First Tap Value Using DFE in Manual Mode
- Transceiver Reconfiguration Controller AEQ Registers
- Transceiver Reconfiguration Controller ATX PLL Calibration Registers
- Transceiver Reconfiguration Controller PLL Reconfiguration
- Transceiver Reconfiguration Controller PLL Reconfiguration Registers
- Transceiver Reconfiguration Controller DCD Calibration Registers
- Transceiver Reconfiguration Controller Channel and PLL Reconfiguration
  - Channel Reconfiguration
  - PLL Reconfiguration
- Transceiver Reconfiguration Controller Streamer Module Registers
  - Mode 0 Streaming a MIF for Reconfiguration
  - Mode 1 Avalon-MM Direct Writes for Reconfiguration
- MIF Generation
- Creating MIFs for Designs that Include Bonded or GT Channels
- MIF Format
- xcvr_diffmifgen Utility
- Reduced MIF Creation
- Changing Transceiver Settings Using Register-Based Reconfiguration
  - Register-Based Write
  - Register-Based Read
- Changing Transceiver Settings Using Streamer-Based Reconfiguration
  - Direct Write Reconfiguration
  - Streamer-Based Reconfiguration
- Pattern Generators for the Stratix V and Arria V GZ Native PHYs
  - Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration
  - Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration
  - Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration
  - Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration
- Understanding Logical Channel Numbering
  - Two PHY IP Core Instances Each with Four Bonded Channels
  - One PHY IP Core Instance with Eight Bonded Channels
- Two PHY IP Core Instances Each with Non-Bonded Channels
- Transceiver Reconfiguration Controller to PHY IP Connectivity
- Merging TX PLLs In Multiple Transceiver PHY Instances
- Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs
- Loopback Modes
17. Transceiver PHY Reset Controller IP Core
- Device Family Support for Transceiver PHY Reset Controller
- Performance and Resource Utilization for Transceiver PHY Reset Controller
- Parameterizing the Transceiver PHY Reset Controller IP
- Transceiver PHY Reset Controller Parameters
- Transceiver PHY Reset Controller Interfaces
- Timing Constraints for Bonded PCS and PMA Channels
18. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
- Parameterizing the Transceiver PLL PHY
- Transceiver PLL Parameters
- Transceiver PLL Signals
19. Analog Parameters Set Using QSF Assignments
- Making QSF Assignments Using the Assignment Editor
- Analog Settings for Arria V Devices
  - Analog Settings for Arria V Devices
  - Analog Settings Having Global or Computed Values for Arria V Devices
- Analog Settings for Arria V GZ Devices
  - Analog Settings for Arria V GZ Devices
  - Analog Settings Having Global or Computed Default Values for Arria V GZ Devices
- Analog Settings for Cyclone V Devices
- Analog Settings for Stratix V Devices
  - Analog PCB Settings for Stratix V Devices
  - Analog Settings Having Global or Computed Default Values for Stratix V Devices
20. Migrating from Stratix IV to Stratix V Devices Overview
- Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers
- Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices
- Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
- Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices
- Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices
- Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices
- Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices
21. Additional Information for the Transceiver PHY IP Core
- Revision History for Previous Releases of the Transceiver PHY IP Core
- How to Contact Altera

Signal Name Direction Description

tx_parallel_data<n>[65] Input

When asserted, indicates that tx_parallel_data<n>

[63:0] is valid and is ready to be written into the TX

FIFO. When deasserted, indicates that tx_parallel_

data<n>[63:0] is invalid and is not written into the

TX FIFO. This signal is the data valid or write enable

port of the TX FIFO. This input must be synchronized

to the tx_coreclkin clock domain.

The Interlaken MAC should gate tx_parallel_

data<n>[65] based on tx_datain_bp<n>. Or, you

can tie tx_datain_bp<n> directly to tx_parallel_

data<n>[65]. For Quartus II releases before 12.0, you

must pre-fill the transmit FIFO so this pin must be

1'b1 when tx_ready is asserted, but before tx_sync_

done is asserted to insert the pre-fill pattern. Do not

use valid data to pre-fill the transmit FIFO. Use the

following Verilog HDL assignment for Quartus II

releases prior to 12.0:

assign tx_parallel_data[65] = (!tx_sync_

done)?1'b1:tx_datain_bp[0];

tx_ready Output When asserted, indicates that the TX interface has

exited the reset state and is ready for service. The tx_

ready latency for the TX interface is 0. A 0 latency

means that the TX FIFO can accept data on the same

clock cycle that tx_ready is asserted. This output is

synchronous to the phy_mgmt_clk clock domain. The

Interlaken MAC must wait for tx_ready before

initiating data transfer (pre-fill pattern or valid user

data) on any lanes. The TX FIFO only captures input

data from the Interlaken MAC when tx_ready and

tx_parallel_data[65] are both asserted. The

beginning of the pre-fill stage is marked by the

assertion of tx_ready, before tx_sync_done is

asserted. The pre-fill stage should terminate when tx_

ready is high and tx_sync_done changes from Logic

0 to Logic 1 state. At this point, TX synchronization is

complete and valid TX data insertion can begin. TX

synchronization is not required for single-lane

variants. Use the following Verilog HDL assignment is

for Quartus versions earlier than 12.0:

assign tx_parallel_data[65] = (!tx_sync_

done)?1'b1:tx_datain_bp[0];

tx_datain_bp<n>

Output

When asserted, indicates that Interlaken TX lane <n>

interface is ready to receive data for transmission. In

7-8

Interlaken PHY Avalon-ST TX Interface

UG-01080

2015.01.19

Altera Corporation

Interlaken PHY IP Core

Send Feedback