User Guide: SDALTEVK HSMC SDI ADAPTER BOARD 9-Jul-09 Version 0.06 SDI Development Kit using National Semiconductor’s LMH0340 serializer and LMH0341 deserializer July 2009 Rev 0.
1 ....Overview 3 2 ....Evaluation Kit (SDALTEVK) Contents 3 ....Hardware Setup 3 5 3.1 CYCLONE III DEVELOPMENT BOARD (MAIN BOARD) DESCRIPTION.................................................................... 6 3.2 SDALTEVK BOARD DESCRIPTION ................................................................................................................. 8 4 ....Software Setup 9 4.1 INSTALLATION ..............................................................................................................
1 Overview The SDALTEVK enables rapid evaluation of the LMH0340/0341 serializer and deserializer in Serial Digital Interface (SDI) applications. Other National devices also highlighted on this board are shown in Table 1.
The following is required to complete the evaluation kit: Altera Cyclone III Development Kit Altera Part Number: DK-DEV-3C120N National Semiconductor SDI compiled .sof file from: http://www.national.com/sdaltevk o Triple Rate Standalone mode with multiple format selection o Triple Rate pass-thru mode with format detection o Pattern selection o Gen-Lock function supported o Register programming supported Altera compiled .sof file from: ftp://ftp.altera.com/outgoing/National_SerDes/an535_1_0.
Hardware Setup The SDALTEVK printed circuit board is designed to interface with the HSMC connector on the Cyclone III Development Boards. Power, control bus, and LVDS bus signals are supplied to the daughter board through the HSMC connector. The Cyclone III FPGA provides the SD/HD/3G SDI and general purpose stacks as well as the control interface to a PC through a USB cable. This evaluation system allows inexpensive FPGAs to deliver up to 3 Gbps on a coax cable.
2.1 Cyclone III Development Board (Main Board) Description The main board has a Cyclone III FPGA. The FPGA provides the SD/HD/3G SDI and general purpose stacks as well as the control interfaces through the supplied example firmware. The daughter board is connected to the main board through the high speed mezzanine connector (HSMC), J8. This connector provides power, control bus, and data bus. The main board communicates to a PC through a USB cable. Figure 3 Cyclone III Development Board 2.
Figure 4 Resistors on HSCM port A Figure 5 Photograph of the back of the Cyclone III board showing location of the 100 Ohm Resistors July 2009 Rev 0.
2.3 SDALTEVK Board Description The HSMC SDI ADAPTER board features the 5:1 LMH0340 serializer IC with integrated cable driver, the 1:5 LMH0341 deserializer IC and the LMH0344 adaptive cable equalizer IC, all highlighted in orange. These devices support SD, HD, or 3G SDI interfaces across 75 ohm coaxial cable, which can interface with the board via BNC connectors J3, J8, J10, or J13. For added testing flexibility, the additional components shown in blue allow for several different clocking schemes.
3 Software Setup 3.1 Installation Make sure the Altera hardware is not connected to the PC. The following installation instructions are for the Windows XP Operating System. Quartus II 8.0 or newer is required to properly operate the SDALTEVK. If the terminal interface is desired then Nios II EDS 8.0 or newer must also be installed on the PC. If an older version of either Quartus II or Nios II EDS is already installed, make sure that it is updated before attempting to use the SDALTEVK.
3.2 Startup Make sure all the software has been installed and the hardware is powered on and connected to the PC. Run Quartus II by either by using the path “C:\altera\80\quartus\bin\quartus.exe” or selecting it from the “altera” folder in the start menu. Once the software has loaded go to the “Tools” menu, and select “Programmer.” Figure 7 Quartus Main Screen July 2009 Rev 0.
This will bring up the programming window shown below. Click on the “Hardware Setup…” button, select the USB-Blaster and click Close. Use the “Add File…” button to select the appropriate bit image to program the FPGA. Make sure that the “Program/Configure” box is checked and that the “Mode” menu has JTAG selected. Press the “Start” button to program the FPGA. Once the progress bar reaches 100%, the SDALTEVK is ready to use. Figure 8 Quartus Programming Screen July 2009 Rev 0.
Once the FPGA has been programmed, the SDALTEVK can be evaluated using the push button interface on the Cyclone III main board. However, if the terminal interface is desired for evaluation, run the Nios II terminal program called “nios2-terminal.exe”. This program can be found in the bin folder of the Nios II root directory, for example “C:\altera\80\nios2eds\bin\nios2-terminal.exe”. If the software loads correctly, a terminal window will appear with a greeting message as shown below.
4 Evaluating Hardware The EVK is designed for flexible and accurate evaluation of LMH0340 and LMH0341. Evaluation can be performed using internal or external stimuli. There is an internal pattern generator implemented in the FPGA that will generate test patterns to verify signal transmission and signal integrity. The pattern generator can generate various types of SD, HD and 3G SDI static video patterns. 4.1 4.1.
4.1.2 Genlock Tests When one of the genlocked modes is selected the system is configured to use an analog sync input to generate genlocked video. The analog reference signal is applied to the EVK through BNC connector J2. If no analog reference is present, the LMH1982 has been configured to automatically switch to the on board oscillator. Figure 11 Genlock Test Setup July 2009 Rev 0.
4.1.3 Video Pass-through Tests In Pass-through Mode the EVK uses the clock recovered by the LMH0341 from the SDI input as the reference clock. The video data is then routed through the FPGA to the LMH0340 for transmission. To configure the EVK for Pass-through Mode connect the source generator to J13 of the deserializer and connect the terminating device to the serializer BNC connector J8. Refer to the diagram below.
4.2.1 Standalone Mode If Standalone Mode is selected from the main menu, a list of available video formats will appear. To select a video format enter the two digit code that appears directly to the left of the format title. Once a format is selected, the terminal will return to the main menu and the SDALTEVK will then be operating, sending a test pattern in the specified SDI video format. Once the two digit code is selected, the Selected format will be displayed followed by the Main Menu.
4.2.2 Analog Sync TPG mode In Analog Sync TPG mode, the user provides an analog sync signal to the analog sync input on the evaluation board (the BNC connector labeled ‘Analog IN’). The LMH1981 extracts the sync information from this signal and passes it to the LMH1982 which generates video clocks for the FPGA, which are then used to clock the LMH0340 serializer and provide an SDI test signal output which is genlocked to the Analog input. Figure 14 Analog Sync TPG Mode 4.2.
4.2.5 Pass Through Mode Before selecting Pass-through Mode from the main menu, apply an SD, HD or 3G SDI video signal from an external source to the SDALTEVK. When Pass-through Mode is selected from the main menu, a message will appear notifying if an input signal of a supported format is detected and return to the main menu. Figure 15 Pass-through Mode Screen July 2009 Rev 0.
4.3 Push Button Based SD/HD/3G SDI Evaluation The EVK can be configured for evaluation by using the push buttons on the Cyclone III main board only. The push button interface allows the EVK to be configured in the same modes as the terminal interface option. However, only the Nios II terminal interface allows for device and FPGA register access. Figure 16 LED and Push Button Locations 4.3.1 Push Button Main Menu After the FPGA has been programmed, the push buttons default to the main menu options.
4.3.2 System Mode The System Mode menu contains the various configuration options for the EVK. Use this menu to configure the EVK into one of the 3 previously discussed modes of operations. PB 0 PB 1 Cancel LED 1 Off PB 2 Genlock LED 2 Blink LED 3 Off LED 4 Off PB 3 Passthrough LED 5 Off LED 6 Standalone LED 7 LED 8 Indicates Current Mode Once a mode has been selected, all of the LEDs will flash and the system will return to the main menu.
5 Frequency Menu This menu configures the push buttons to cycle through supported clock frequencies. Users must select a video format with a compatible frequency in order for the system to be configured. If the system is in Standalone Mode and a valid combination is selected, the LEDs will flash once to indicate successful configuration. In other mode the video format and frequency settings are ignored.
5.1.1 Miscellaneous Registers: Hex Address: 00 5.1.2 Name IPT ID Description ID Code (1234 Hex) Bits 15:0 Bit Description ID Code Description Status bits of various system resets Bits 15:4 Bit Description Reserved Reset Registers Hex Address: 01 Name RESET STATUS 02 5.1.
Hex Address: Name Description Bits Bit Description 7:4 Reserved 3:0 05 CRC STATUS CRC Error Check 15 Format Detected: 0000 0 PAL I50 0001 1 NTSC I59 0010 2 P720 50 0011 3 P720 60 0100 4 S1080 24 0101 5 I1080 50 0110 6 I1080 60 0111 7 P1080 24 1000 8 P1080 25 1001 9 P1080 30 1010 A P1080 50 1011 B P1080 60 Reserved 06 CRC CONTROL CRC Check Control 14:0 15:3 CRC Error Count Reserved 07 EDH STATUS 1 EDH Error Check Status Reg 2 Select Holdover Mode 1 Reset Status flags 0 15 Reset CRC
Hex Address: 09 Name EDHAP COUNT 0A EDH FF COUNT 0B AUDIO IN STATUS 0C SMPTE35234 0D SMPTE35212 0E AUDIO IN CONTROL Description Extended Count of EDH Errors Extended Count of EDH Errors Input Audio (Over SDI) Status Extracted SMPTE352 Bytes 3, 4 Extracted SMPTE352 Bytes 1, 2 I2S Output Control Bits 15:0 15:0 15:4 3 Group 4 detected 2 Group 3 detected 1 Group 2 detected 0 15:0 Group 1 detected SMPTE352 Bytes 4 and 3 15:0 SMPTE352 Bytes 2 and 1 15:1 Reserved 0 5.1.
Hex Address: Name CONTROL Description Bits 2:0 14 15 DP AUDIO OUT CONTROL Control Audio Insertion Module 15:8 Selected Frequency, see RX VID FREQ for values AFN ( Audio Frame Count) Max 7:4 Audio control packet rate 3 Reserved 2 1:0 15:0 Select internal tone generator (0) or I2S input (1) Select output audio group Reserved 15:8 Channel 1 Frequency 7:0 15:8 Channel 2 Frequency Channel 3 Frequency AUDIO OUT STATUS AUDIO OUT INCR 1 Controls Increment Rate for Internal Tone Generator 17 A
Hex Address: Name 1B SMPTE 352 INSERT CONTROL LINE PATTERN UPDATE 1 LINE PATTERN UPDATE 2 LINE PATTERN UPDATE ADDR 1C 1D 1E 5.1.
Hex Address: Name Description Bits 11 10 Genlock reference present 9 Genlock No Lock 8 Genlock No Ref 7 Reserved 6:4 3:0 25 VFORMAT STATUS Looks for Matching VFORMAT Sequences from the LMH1981 and Decodes Them 15 14:12 11 10:0 26 LINE TIME COUNT 27 STATUS GENFORMAT Used to Determine Format.
Hex Address: July 2009 Name Description Bits 7:0 Bit Description Counts when timing is resynchronized Rev 0.
5.2 Supported Test Patterns The following test patterns are available from the SDI firmware in all SD, HD and 3G formats: 100% Color Bars Frequency Sweep Matrix Pathological Black Luma Ramp SMPTE 75% Color Bars Y/C Full Range Ramp SMPTE RP219 Color Bars Luma Pulse & Bar July 2009 Rev 0.
6 Documentation Additional SDALTEVK documentation can be found on the EVK website. 7 Schematics, BOMs, and Data Sheets All of the schematics, BOMs, and data sheets for the SDALTEVK can be found on the EVK website. 8 Reference FPGA IP The reference FPGA IP source code and documentation can be found on EVK website. 9 Up to Date Information For up to date information check this URL http://www.national.com/sdaltevk 10 Part Numbers Cyclone III Development Board: DK-DEV-3C120N http://www.altera.
Revision History Release 0.00 0.01 0.02 Date 8-19-2008 8-19-2008 8-25-2008 0.03 8-28-2008 N. Unger 0.04 0.05 9-02-2008 N. Unger 9-03-2008 N. Unger 0.06 07-09-2009 M. Sauerwald July 2009 Who M. Wolfe M. Wolfe N.
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