User's Manual

130 AMD Athlon™ Processor Microarchitecture
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
AMD Athlon™ Processor Microarchitecture
The innovative AMD Athlon processor microarchitecture
approach implements the x86 instruction set by processing
simpler operations (OPs) instead of complex x86 instructions.
These OPs are specially designed to include direct support for
the x86 instructions while observing the high-performance
principles of fixed-length encoding, regularized instruction
fields, and a large register set. Instead of executing complex
x86 instructions, which have lengths from 1 to 15 bytes, the
AMD Athlon processor executes the simpler fixed-length OPs,
while maintaining the instruction coding efficiencies found in
x86 programs. The enhanced microarchitecture used in the
AMD Athlon processor enables higher processor core
performance and promotes straightforward extendibility for
future designs.
Superscalar Processor
The AMD Athlon processor is an aggressive, out-of-order,
three-way superscalar x86 processor. It can fetch, decode, and
issue up to three x86 instructions per cycle with a centralized
instruction control unit (ICU) and two independent instruction
schedulers— an integer scheduler and a floating-point
scheduler. These two schedulers can simultaneously issue up to
nine OPs to the three general-purpose integer execution units
(IEUs), three address-generation units (AGUs), and three
floating-point/3DNow!™/MMX™ execution units. The
AMD Athlon moves integer instructions down the integer
execution pipeline, which consists of the integer scheduler and
the IEUs, as shown in Figure 1 on page 131. Floating-point
instructions are handled by the floating-point execution
pipeline, which consists of the floating-point scheduler and the
x87/3DNow!/MMX execution units.