User's Manual

AMD Athlon™ Processor Microarchitecture 139
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
L2 Cache Controller
The AMD Athlon processor contains a very flexible onboard L2
controller. It uses an independent backside bus to access up to
8-Mbytes of industry-standard SRAMs. There are full on-chip
tags for a 512-Kbyte cache, while larger sizes use a partial tag
system. In addition, there is a two-level data TLB structure. The
first-level TLB is fully associative and contains 32 entries (24
that map 4-Kbyte pages and eight that map 2-Mbyte or 4-Mbyte
pages). The second-level TLB is four-way set associative and
contains 256 entries, which can map 4-Kbyte pages.
Write Combining
See Appendix C, “Implementation of Write Combining” on
page 155 for detailed information about write combining.
AMD Athlon™ System Bus
The AMD Athlon system bus is a high-speed bus that consists of
a pair of unidirectional 13-bit address and control channels and
a bidirectional 64-bit data bus. The AMD Athlon system bus
supports low-voltage swing, multiprocessing, clock forwarding,
and fast data transfers. The clock forwarding technique is used
to deliver data on both edges of the reference clock, therefore
doubling the transfer speed. A four-entry 64-byte write buffer is
integrated into the BIU. The write buffer improves bus
utilization by combining multiple writes into a single large
write cycle. By using the AMD Athlon system bus, the
AMD Athlon processor can transfer data on the 64-bit data bus
at 200 MHz, which yields an effective throughput of 1.6-Gbyte
per second.