User's Manual

142 Fetch and Decode Pipeline Stages
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Figure 5. Fetch/Scan/Align/Decode Pipeline Hardware
The most common x86 instructions flow through the DirectPath
pipeline stages and are decoded by hardware. The less common
instructions, which require microcode assistance, flow through
the VectorPath. Although the DirectPath decodes the common
x86 instructions, it also contains VectorPath instruction data,
which allows it to maintain dispatch order at the end of cycle 5.
Figure 6. Fetch/Scan/Align/Decode Pipeline Stages
1
23 4 5 6
Entry
Point
Decode
I-CACHE
Quadword
Queue
FETCH SCAN ALIGN1/
MECTL
ALIGN2/
MEROM
EDEC/
MEDEC
MROM
3
MacroOps
Decode
Decode
Decode
Decode
Decode
Decode
Decode
Decode
Decode
16 bytes
DirectPath
DirectPath
VectorPath
VectorPath
IDEC
FETCH SCAN
ALIGN1 ALIGN2 EDEC
1 2
3
MECTL MEROM MESEQ
DirectPath
VectorPath
4
5
IDEC
6