User's Manual

Write-Combining Operations 157

22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization

signature in register EAX, where EAX[11–8] contains the

instruction family code. For the AMD Athlon processor, the

instruction family code is six.

2. In addition, the presence of the MTRRs is indicated by bit

12 and the presence of the PAT extension is indicated by bit

16 of the extended features bits returned in the EDX

Processor Recognition Application Note, order# 20734 for

more details on the CPUID instruction.

3. Write combining is controlled by the MTRRs and PAT.

Write combining should be enabled for the appropriate

memory ranges. The AMD Athlon processor MTRRs and

PAT are compatible with the Pentium

II.

Write-Combining Operations

In order to improve system performance, the AMD Athlon

processor aggressively combines multiple memory-write cycles

of any data size that address locations within a 64-byte write

buffer that is aligned to a cache-line boundary. The data sizes

can be bytes, words, longwords, or quadwords.

WC memory type writes can be combined in any order up to a

full 64-byte sized write buffer.

WT memory type writes can only be combined up to a fully

aligned quadword in the 64-byte buffer, and must be combined

contiguously in ascending order. Combining may be opened at

any byte boundary in a quadword, but is closed by a write that is

either not “contiguous and ascending” or fills byte 7.

All other memory types for stores that go through the write

buffer (UC and WP) cannot be combined.

Combining is able to continue until interrupted by one of the

conditions listed in Table 9 on page 158. When combining is

interrupted, one or more bus commands are issued to the

system for that write buffer, as described by Table 10 on

page 159.