User's Manual

158 Write-Combining Operations
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Table 9. Write Combining Completion Events
Event Comment
Non-WB write outside of
current buffer
The first non-WB write to a different cache block address
closes combining for previous writes. WB writes do not affect
write combining. Only one line-sized buffer can be open for
write combining at a time. Once a buffer is closed for write
combining, it cannot be reopened for write combining.
I/O Read or Write
Any IN/INS or OUT/OUTS instruction closes combining. The
implied memory type for all IN/OUT instructions is UC,
which cannot be combined.
Serializing instructions
Any serializing instruction closes combining. These
instructions include: MOVCRx, MOVDRx, WRMSR, INVD,
INVLPG, WBINVD, LGDT, LLDT, LIDT, LTR, CPUID, IRET, RSM,
INIT, HALT.
Flushing instructions Any flush instruction causes the WC to complete.
Locks
Any instruction or processor operation that requires a cache
or bus lock closes write combining before starting the lock.
Writes within a lock can be combined.
Uncacheable Read
A UC read closes write combining. A WC read closes
combining only if a cache block address match occurs
between the WC read and a write in the write buffer.
Different memory type
Any WT write while write-combining for WC memory or any
WC write while write combining for WT memory closes write
combining.
Buffer full
Write combining is closed if all 64 bytes of the write buffer
are valid.
WT time-out
If 16 processor clocks have passed since the most recent
write for WT write combining, write combining is closed.
There is no time-out for WC write combining.
WT write fills byte 7
Write combining is closed if a write fills the most significant
byte of a quadword, which includes writes that are
misaligned across a quadword boundary. In the misaligned
case, combining is closed by the LS part of the misaligned
write and combining is opened by the MS part of the
misaligned store.
WT Nonsequential
If a subsequent WT write is not in ascending sequential
order, the write combining completes. WC writes have no
addressing constraints within the 64-byte line being
combined.
TLB AD bit set
Write combining is closed whenever a TLB reload sets the
accessed (A) or dirty (D) bits of a Pde or Pte.