User's Manual

Write-Combining Operations 159
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Sending Write-Buffer Data to the System
Once write combining is closed for a 64-byte write buffer, the
contents of the write buffer are eligible to be sent to the system
as one or more AMD Athlon system bus commands. Table 10
lists the rules for determining what system commands are
issued for a write buffer, as a function of the alignment of the
valid buffer data.
Table 10. AMD Athlon™ System Bus Commands Generation Rules
1. If all eight quadwords are either full (8 bytes valid) or empty (0 bytes valid), a
Write-Quadword system command is issued, with an 8-byte mask representing
which of the eight quadwords are valid. If this case is true, do not proceed to the
next rule.
2. If all longwords are either full (4 bytes valid) or empty (0 bytes valid), a
Write-Longword system command is issued for each 32-byte buffer half that
contains at least one valid longword. The mask for each Write-Longword system
command indicates which longwords are valid in that 32-byte write buffer half. If
this case is true, do not proceed to the next rule.
3. Sequence through all eight quadwords of the write buffer, from quadword 0 to
quadword 7. Skip over a quadword if no bytes are valid. Issue a Write-Quad system
command if all bytes are valid, asserting one mask bit. Issue a Write-Longword
system command if the quadword contains one aligned longword, asserting one
mask bit. Otherwise, issue a Write-Byte system command if there is at least one
valid byte, asserting a mask bit for each valid byte.