User's Manual

Performance Counter Usage 163
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Unit Mask Field (Bits
8—15)
These bits are used to further qualify the event selected in the
event select field. For example, for some cache events, the mask
is used as a MESI-protocol qualifier of cache states. See
Table 11 on page 164 for a list of unit masks and their 8-bit
codes.
USR (User Mode) Flag
(Bit 16)
Events are counted only when the processor is operating at
privilege levels 1, 2 or 3. This flag can be used in conjunction
with the OS flag.
OS (Operating System
Mode) Flag (Bit 17)
Events are counted only when the processor is operating at
privilege level 0. This flag can be used in conjunction with the
USR flag.
E (Edge Detect) Flag
(Bit 18)
When this flag is set, edge detection of events is enabled. The
processor counts the number of negated-to-asserted transitions
of any condition that can be expressed by the other fields. The
mechanism is limited in that it does not permit back-to-back
assertions to be distinguished. This mechanism allows software
to measure not only the fraction of time spent in a particular
state, but also the average length of time spent in such a state
(for example, the time spent waiting for an interrupt to be
serviced).
PC (Pin Control) Flag
(Bit 19)
When this flag is set, the processor toggles the PMi pins when
the counter overflows. When this flag is clear, the processor
toggles the PMi pins and increments the counter when
performance monitoring events occur. The toggling of a pin is
defined as assertion of the pin for one bus clock followed by
negation.
INT (APIC Interrupt
Enable) Flag (Bit 20)
When this flag is set, the processor generates an interrupt
through its local APIC on counter overflow.
EN (Enable Counter)
Flag (Bit 22)
This flag enables/disables the PerfEvtSeln MSR. When set,
performance counting is enabled for this counter. When clear,
this counter is disabled.
INV (Invert) Flag (Bit
23)
By inverting the Counter Mask Field, this flag inverts the result
of the counter comparison, allowing both greater than and less
than comparisons.
Counter Mask Field
(Bits 31–24)
For events which can have multiple occurrences within one
clock, this field is used to set a threshold. If the field is non-zero,
the counter increments each time the number of events is