User's Manual

Memory Type Range Register (MTRR) Mechanism 175
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
MTRR Default Type Register Format. The MTRR default type register
is defined as follows.
Figure 14. MTRR Default Type Register Format
E MTRRs are enabled when set. All MTRRs (both fixed and
variable range) are disabled when clear, and all of
physical memory is mapped as uncacheable memory
(reset state = 0).
FE Fixed-range MTRRs are enabled when set. All MTRRs
are disabled when clear. When the fixed-range MTRRs
are enabled and an overlap occurs with a variable-range
MTRR, the fixed-range MTRR takes priority (reset state
= 0).
Type Defines the default memory type (reset state = 0). See
Table 13 for more details.
8
73210
63 91011
F
E
Type
Symbol Description Bits
EMTRRs Enabled 11
FE Fixed Range Enabled 10
Type Default Memory Type 7–0
Reserved
E