User's Manual

176 Memory Type Range Register (MTRR) Mechanism
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Note that if two or more variable memory ranges match then
the interactions are defined as follows:
1. If the memory types are identical, then that memory type is
used.
2. If one or more of the memory types is UC, the UC memory
type is used.
3. If one or more of the memory types is WT and the only other
matching memory type is WB then the WT memory type is
used.
4. Otherwise, if the combination of memory types is not listed
above then the behavior of the processor is undefined.
MTRR Overlapping The Intel documentation (P6/PII) states that the mapping of
large pages into regions that are mapped with differing memory
types can result in undefined behavior. However, testing shows
that these processors decompose these large pages into 4-Kbyte
pages.
When a large page (2 Mbytes/4 Mbytes) mapping covers a
region that contains more than one memory type (as mapped by
the MTRRs), the AMD Athlon processor does not suppress the
caching of that large page mapping and only caches the
mapping for just that 4-Kbyte piece in the 4-Kbyte TLB.
Therefore, the AMD Athlon processor does not decompose
large pages under these conditions. The fixed range MTRRs are
Table 13. Standard MTRR Types and Properties
Memory Type
Encoding in
MTRR
Internally
Cacheable
Writeback
Cacheable
Allows
Speculative
Reads
Memory Ordering Model
Uncacheable (UC) 0 No No No Strong ordering
Write Combining (WC) 1 No No Yes Weak ordering
Reserved 2 - - - -
Reserved 3 - - - -
Writethrough (WT) 4 Yes No Yes Speculative ordering
Write Protected (WP) 5
Yes, reads
No, Writes
No Yes Speculative ordering
Writeback (WB) 6 Yes Yes Yes Speculative ordering
Reserved 7-255 - - - -