User's Manual

Page Attribute Table (PAT) 185
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
MTRR MSR Format This table defines the model-specific registers related to the
memory type range register implementation. All MTRRs are
defined to be 64 bits.
Table 18. MTRR-Related Model-Specific Register (MSR) Map
Register Address Register Name Description
0FEh MTRRcap See “MTRR Capability Register Format” on page 174.
200h MTRR Base0 See “MTRRphysBasen Register Format” on page 183.
201h MTRR Mask0 See “MTRRphysMaskn Register Format” on page 184.
202h MTRR Base1
203h MTRR Mask1
204h MTRR Base2
205h MTRR Mask2
206h MTRR Base3
207h MTRR Mask3
208h MTRR Base4
209h MTRR Mask4
20Ah MTRR Base5
20Bh MTRR Mask5
20Ch MTRR Base6
20Dh MTRR Mask6
20Eh MTRR Base7
20Fh MTRR Mask7
250h MTRRFIX64k_00000
See “MTRR Fixed-Range Register Format” on page 182.
258h MTRRFIX16k_80000
259h MTRRFIX16k_A0000
268h MTRRFIX4k_C0000
269h MTRRFIX4k_C8000
26Ah MTRRFIX4k_D0000
26Bh MTRRFIX4k_D8000
26Ch MTRRFIX4k_E0000
26Dh MTRRFIX4k_E8000
26Eh MTRRFIX4k_F0000
26Fh MTRRFIX4k_F8000
2FFh MTRRdefType See “MTRR Default Type Register Format” on page 175.