User's Manual

Instruction Dispatch and Execution Resources 191
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
BT mem16/32, imm8 0Fh BAh mm-100-xxx DirectPath
BTC mreg16/32, reg16/32 0Fh BBh 11-xxx-xxx VectorPath
BTC mem16/32, reg16/32 0Fh BBh mm-xxx-xxx VectorPath
BTC mreg16/32, imm8 0Fh BAh 11-111-xxx VectorPath
BTC mem16/32, imm8 0Fh BAh mm-111-xxx VectorPath
BTR mreg16/32, reg16/32 0Fh B3h 11-xxx-xxx VectorPath
BTR mem16/32, reg16/32 0Fh B3h mm-xxx-xxx VectorPath
BTR mreg16/32, imm8 0Fh BAh 11-110-xxx VectorPath
BTR mem16/32, imm8 0Fh BAh mm-110-xxx VectorPath
BTS mreg16/32, reg16/32 0Fh ABh 11-xxx-xxx VectorPath
BTS mem16/32, reg16/32 0Fh ABh mm-xxx-xxx VectorPath
BTS mreg16/32, imm8 0Fh BAh 11-101-xxx VectorPath
BTS mem16/32, imm8 0Fh BAh mm-101-xxx VectorPath
CALL full pointer 9Ah VectorPath
CALL near imm16/32 E8h VectorPath
CALL mem16:16/32 FFh 11-011-xxx VectorPath
CALL near mreg32 (indirect) FFh 11-010-xxx VectorPath
CALL near mem32 (indirect) FFh mm-010-xxx VectorPath
CBW/CWDE 98h DirectPath
CLC F8h DirectPath
CLD FCh VectorPath
CLI FAh VectorPath
CLTS 0Fh 06h VectorPath
CMC F5h DirectPath
CMOVA/CMOVNBE reg16/32, reg16/32 0Fh 47h 11-xxx-xxx DirectPath
CMOVA/CMOVNBE reg16/32, mem16/32 0Fh 47h mm-xxx-xxx DirectPath
CMOVAE/CMOVNB/CMOVNC reg16/32, mem16/32 0Fh 43h 11-xxx-xxx DirectPath
CMOVAE/CMOVNB/CMOVNC mem16/32,
mem16/32
0Fh 43h mm-xxx-xxx DirectPath
CMOVB/CMOVC/CMOVNAE reg16/32, reg16/32 0Fh 42h 11-xxx-xxx DirectPath
CMOVB/CMOVC/CMOVNAE mem16/32, reg16/32 0Fh 42h mm-xxx-xxx DirectPath
CMOVBE/CMOVNA reg16/32, reg16/32 0Fh 46h 11-xxx-xxx DirectPath
CMOVBE/CMOVNA reg16/32, mem16/32 0Fh 46h mm-xxx-xxx DirectPath
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type