User's Manual

Instruction Dispatch and Execution Resources 197
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
LOOPE/LOOPZ disp8 E1h VectorPath
LOOPNE/LOOPNZ disp8 E0h VectorPath
LSL reg16/32, mreg16/32 0Fh 03h 11-xxx-xxx VectorPath
LSL reg16/32, mem16/32 0Fh 03h mm-xxx-xxx VectorPath
LSS reg16/32, mem32/48 0Fh B2h mm-xxx-xxx VectorPath
LTR mreg16 0Fh 00h 11-011-xxx VectorPath
LTR mem16 0Fh 00h mm-011-xxx VectorPath
MOV mreg8, reg8 88h 11-xxx-xxx DirectPath
MOV mem8, reg8 88h mm-xxx-xxx DirectPath
MOV mreg16/32, reg16/32 89h 11-xxx-xxx DirectPath
MOV mem16/32, reg16/32 89h mm-xxx-xxx DirectPath
MOV reg8, mreg8 8Ah 11-xxx-xxx DirectPath
MOV reg8, mem8 8Ah mm-xxx-xxx DirectPath
MOV reg16/32, mreg16/32 8Bh 11-xxx-xxx DirectPath
MOV reg16/32, mem16/32 8Bh mm-xxx-xxx DirectPath
MOV mreg16, segment reg 8Ch 11-xxx-xxx VectorPath
MOV mem16, segment reg 8Ch mm-xxx-xxx VectorPath
MOV segment reg, mreg16 8Eh 11-xxx-xxx VectorPath
MOV segment reg, mem16 8Eh mm-xxx-xxx VectorPath
MOV AL, mem8 A0h DirectPath
MOV EAX, mem16/32 A1h DirectPath
MOV mem8, AL A2h DirectPath
MOV mem16/32, EAX A3h DirectPath
MOV AL, imm8 B0h DirectPath
MOV CL, imm8 B1h DirectPath
MOV DL, imm8 B2h DirectPath
MOV BL, imm8 B3h DirectPath
MOV AH, imm8 B4h DirectPath
MOV CH, imm8 B5h DirectPath
MOV DH, imm8 B6h DirectPath
MOV BH, imm8 B7h DirectPath
MOV EAX, imm16/32 B8h DirectPath
MOV ECX, imm16/32 B9h DirectPath
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type