User's Manual

Instruction Dispatch and Execution Resources 207
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
XADD mreg8, reg8 0Fh C0h 11-100-xxx VectorPath
XADD mem8, reg8 0Fh C0h mm-100-xxx VectorPath
XADD mreg16/32, reg16/32 0Fh C1h 11-101-xxx VectorPath
XADD mem16/32, reg16/32 0Fh C1h mm-101-xxx VectorPath
XCHG reg8, mreg8 86h 11-xxx-xxx VectorPath
XCHG reg8, mem8 86h mm-xxx-xxx VectorPath
XCHG reg16/32, mreg16/32 87h 11-xxx-xxx VectorPath
XCHG reg16/32, mem16/32 87h mm-xxx-xxx VectorPath
XCHG EAX, EAX 90h DirectPath
XCHG EAX, ECX 91h VectorPath
XCHG EAX, EDX 92h VectorPath
XCHG EAX, EBX 93h VectorPath
XCHG EAX, ESP 94h VectorPath
XCHG EAX, EBP 95h VectorPath
XCHG EAX, ESI 96h VectorPath
XCHG EAX, EDI 97h VectorPath
XLAT D7h VectorPath
XOR mreg8, reg8 30h 11-xxx-xxx DirectPath
XOR mem8, reg8 30h mm-xxx-xxx DirectPath
XOR mreg16/32, reg16/32 31h 11-xxx-xxx DirectPath
XOR mem16/32, reg16/32 31h mm-xxx-xxx DirectPath
XOR reg8, mreg8 32h 11-xxx-xxx DirectPath
XOR reg8, mem8 32h mm-xxx-xxx DirectPath
XOR reg16/32, mreg16/32 33h 11-xxx-xxx DirectPath
XOR reg16/32, mem16/32 33h mm-xxx-xxx DirectPath
XOR AL, imm8 34h DirectPath
XOR EAX, imm16/32 35h DirectPath
XOR mreg8, imm8 80h 11-110-xxx DirectPath
XOR mem8, imm8 80h mm-110-xxx DirectPath
XOR mreg16/32, imm16/32 81h 11-110-xxx DirectPath
XOR mem16/32, imm16/32 81h mm-110-xxx DirectPath
XOR mreg16/32, imm8 (sign extended) 83h 11-110-xxx DirectPath
XOR mem16/32, imm8 (sign extended) 83h mm-110-xxx DirectPath
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type