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210 Instruction Dispatch and Execution Resources

AMD Athlon™ Processor x86 Code Optimization

22007E/0—November 1999

PSRAW mmreg1, mmreg2 0Fh E1h 11-xxx-xxx DirectPath FADD/FMUL

PSRAW mmreg, mem64 0Fh E1h mm-xxx-xxx DirectPath FADD/FMUL

PSRAW mmreg, imm8 0Fh 71h 11-100-xxx DirectPath FADD/FMUL

PSRAD mmreg1, mmreg2 0Fh E2h 11-xxx-xxx DirectPath FADD/FMUL

PSRAD mmreg, mem64 0Fh E2h mm-xxx-xxx DirectPath FADD/FMUL

PSRAD mmreg, imm8 0Fh 72h 11-100-xxx DirectPath FADD/FMUL

PSRLD mmreg1, mmreg2 0Fh D2h 11-xxx-xxx DirectPath FADD/FMUL

PSRLD mmreg, mem64 0Fh D2h mm-xxx-xxx DirectPath FADD/FMUL

PSRLD mmreg, imm8 0Fh 72h 11-010-xxx DirectPath FADD/FMUL

PSRLQ mmreg1, mmreg2 0Fh D3h 11-xxx-xxx DirectPath FADD/FMUL

PSRLQ mmreg, mem64 0Fh D3h mm-xxx-xxx DirectPath FADD/FMUL

PSRLQ mmreg, imm8 0Fh 73h 11-010-xxx DirectPath FADD/FMUL

PSRLW mmreg1, mmreg2 0Fh D1h 11-xxx-xxx DirectPath FADD/FMUL

PSRLW mmreg, mem64 0Fh D1h mm-xxx-xxx DirectPath FADD/FMUL

PSRLW mmreg, imm8 0Fh 71h 11-010-xxx DirectPath FADD/FMUL

PSUBB mmreg1, mmreg2 0Fh F8h 11-xxx-xxx DirectPath FADD/FMUL

PSUBB mmreg, mem64 0Fh F8h mm-xxx-xxx DirectPath FADD/FMUL

PSUBD mmreg1, mmreg2 0Fh FAh 11-xxx-xxx DirectPath FADD/FMUL

PSUBD mmreg, mem64 0Fh FAh mm-xxx-xxx DirectPath FADD/FMUL

PSUBSB mmreg1, mmreg2 0Fh E8h 11-xxx-xxx DirectPath FADD/FMUL

PSUBSB mmreg, mem64 0Fh E8h mm-xxx-xxx DirectPath FADD/FMUL

PSUBSW mmreg1, mmreg2 0Fh E9h 11-xxx-xxx DirectPath FADD/FMUL

PSUBSW mmreg, mem64 0Fh E9h mm-xxx-xxx DirectPath FADD/FMUL

PSUBUSB mmreg1, mmreg2 0Fh D8h 11-xxx-xxx DirectPath FADD/FMUL

PSUBUSB mmreg, mem64 0Fh D8h mm-xxx-xxx DirectPath FADD/FMUL

PSUBUSW mmreg1, mmreg2 0Fh D9h 11-xxx-xxx DirectPath FADD/FMUL

PSUBUSW mmreg, mem64 0Fh D9h mm-xxx-xxx DirectPath FADD/FMUL

PSUBW mmreg1, mmreg2 0Fh F9h 11-xxx-xxx DirectPath FADD/FMUL

PSUBW mmreg, mem64 0Fh F9h mm-xxx-xxx DirectPath FADD/FMUL

PUNPCKHBW mmreg1, mmreg2 0Fh 68h 11-xxx-xxx DirectPath FADD/FMUL

PUNPCKHBW mmreg, mem64 0Fh 68h mm-xxx-xxx DirectPath FADD/FMUL

Table 20. MMX™ Instructions (Continued)

Instruction Mnemonic

Prefix

Byte(s)

First

Byte

ModR/M

Byte

Decode

Type

FPU Pipe(s) Notes

Notes:

1. Bits 2, 1, and 0 of the modR/M byte select the integer register.