User's Manual

212 Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
PMINSW mmreg, mem64 0Fh EAh mm-xxx-xxx DirectPath FADD/FMUL
PMINUB mmreg1, mmreg2 0Fh DAh 11-xxx-xxx DirectPath FADD/FMUL
PMINUB mmreg, mem64 0Fh DAh mm-xxx-xxx DirectPath FADD/FMUL
PMOVMSKB reg32, mmreg 0Fh D7h VectorPath
PMULHUW mmreg1, mmreg2 0Fh E4h 11-xxx-xxx DirectPath FMUL
PMULHUW mmreg, mem64 0Fh E4h mm-xxx-xxx DirectPath FMUL
PSADBW mmreg1, mmreg2 0Fh F6h 11-xxx-xxx DirectPath FADD
PSADBW mmreg, mem64 0Fh F6h mm-xxx-xxx DirectPath FADD
PSHUFW mmreg1, mmreg2, imm8 0Fh 70h DirectPath FADD/FMUL
PSHUFW mmreg, mem64, imm8 0Fh 70h DirectPath FADD/FMUL
PREFETCHNTA mem8 0Fh 18h DirectPath - 1
PREFETCHT0 mem8 0Fh 18h DirectPath - 1
PREFETCHT1 mem8 0Fh 18h DirectPath - 1
PREFETCHT2 mem8 0Fh 18h DirectPath - 1
SFENCE 0Fh AEh VectorPath -
Table 22. Floating-Point Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Note
F2XM1 D9h F0h VectorPath
FABS D9h E1h DirectPath FMUL
FADD ST, ST(i) D8h 11-000-xxx DirectPath FADD 1
FADD [mem32real] D8h mm-000-xxx DirectPath FADD
FADD ST(i), ST DCh 11-000-xxx DirectPath FADD 1
FADD [mem64real] DCh mm-000-xxx DirectPath FADD
FADDP ST(i), ST DEh 11-000-xxx DirectPath FADD 1
FBLD [mem80] DFh mm-100-xxx VectorPath
FBSTP [mem80] DFh mm-110-xxx VectorPath
FCHS D9h E0h DirectPath FMUL
FCLEX DBh E2h VectorPath
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
Table 21. MMX™ Extensions (Continued)
Instruction Mnemonic
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Notes
Notes:
1. For the PREFETCHNTA/T0/T1/T2 instructions, the mem8 value refers to an address in the 64-byte line that will be prefetched.