User's Manual

218 Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
PFRSQRT mmreg, mem64 0Fh, 0Fh 97h mm-xxx-xxx DirectPath FMUL
PFSUB mmreg1, mmreg2 0Fh, 0Fh 9Ah 11-xxx-xxx DirectPath FADD
PFSUB mmreg, mem64 0Fh, 0Fh 9Ah mm-xxx-xxx DirectPath FADD
PFSUBR mmreg1, mmreg2 0Fh, 0Fh AAh 11-xxx-xxx DirectPath FADD
PFSUBR mmreg, mem64 0Fh, 0Fh AAh mm-xxx-xxx DirectPath FADD
PI2FD mmreg1, mmreg2 0Fh, 0Fh 0Dh 11-xxx-xxx DirectPath FADD
PI2FD mmreg, mem64 0Fh, 0Fh 0Dh mm-xxx-xxx DirectPath FADD
PMULHRW mmreg1, mmreg2 0Fh, 0Fh B7h 11-xxx-xxx DirectPath FMUL
PMULHRW mmreg1, mem64 0Fh, 0Fh B7h mm-xxx-xxx DirectPath FMUL
PREFETCH mem8 0Fh 0Dh mm-000-xxx DirectPath - 1, 2
PREFETCHW mem8 0Fh 0Dh mm-001-xxx DirectPath - 1, 2
Table 23. 3DNow!™ Instructions (Continued)
Instruction Mnemonic
Prefix
Byte(s)
imm8
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Note
Notes:
1. For the PREFETCH and PREFETCHW instructions, the mem8 value refers to an address in the 64-byte line that will be
prefetched.
2. The byte listed in the column titled ‘imm8’ is actually the opcode byte.
Table 24. 3DNow!™ Extensions
Instruction Mnemonic
Prefix
Byte(s)
imm8
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Note
PF2IW mmreg1, mmreg2 0Fh, 0Fh 1Ch 11-xxx-xxx DirectPath FADD
PF2IW mmreg, mem64 0Fh, 0Fh 1Ch mm-xxx-xxx DirectPath FADD
PFNACC mmreg1, mmreg2 0Fh, 0Fh 8Ah 11-xxx-xxx DirectPath FADD
PFNACC mmreg, mem64 0Fh, 0Fh 8Ah mm-xxx-xxx DirectPath FADD
PFPNACC mmreg1, mmreg2 0Fh, 0Fh 8Eh 11-xxx-xxx DirectPath FADD
PFPNACC mmreg, mem64 0Fh, 0Fh 8Eh mm-xxx-xxx DirectPath FADD
PI2FW mmreg1, mmreg2 0Fh, 0Fh 0Ch 11-xxx-xxx DirectPath FADD
PI2FW mmreg, mem64 0Fh, 0Fh 0Ch mm-xxx-xxx DirectPath FADD
PSWAPD mmreg1, mmreg2 0Fh, 0Fh BBh 11-xxx-xxx DirectPath FADD/FMUL
PSWAPD mmreg, mem64 0Fh, 0Fh BBh mm-xxx-xxx DirectPath FADD/FMUL