User's Manual

232 VectorPath Instructions
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
DIV EAX, mem16/32
ENTER
IDIV mreg8
IDIV mem8
IDIV EAX, mreg16/32
IDIV EAX, mem16/32
IMUL reg16/32, imm16/32
IMUL reg16/32, mreg16/32, imm16/32
IMUL reg16/32, mem16/32, imm16/32
IMUL reg16/32, imm8 (sign extended)
IMUL reg16/32, mreg16/32, imm8 (signed)
IMUL reg16/32, mem16/32, imm8 (signed)
IMUL AX, AL, mreg8
IMUL AX, AL, mem8
IMUL EDX:EAX, EAX, mreg16/32
IMUL EDX:EAX, EAX, mem16/32
IMUL reg16/32, mreg16/32
IMUL reg16/32, mem16/32
IN AL, imm8
IN AX, imm8
IN EAX, imm8
IN AL, DX
IN AX, DX
IN EAX, DX
INVD
INVLPG
JCXZ/JEC short disp8
JMP far disp32/48 (direct)
JMP far mem32 (indirect)
JMP far mreg32 (indirect)
LAHF
LAR reg16/32, mreg16/32
LAR reg16/32, mem16/32
LDS reg16/32, mem32/48
Table 29. VectorPath Integer Instructions (Continued)
Instruction Mnemonic
LEA reg16, mem16/32
LEAVE
LES reg16/32, mem32/48
LFS reg16/32, mem32/48
LGDT mem48
LGS reg16/32, mem32/48
LIDT mem48
LLDT mreg16
LLDT mem16
LMSW mreg16
LMSW mem16
LODSB AL, mem8
LODSW AX, mem16
LODSD EAX, mem32
LOOP disp8
LOOPE/LOOPZ disp8
LOOPNE/LOOPNZ disp8
LSL reg16/32, mreg16/32
LSL reg16/32, mem16/32
LSS reg16/32, mem32/48
LTR mreg16
LTR mem16
MOV mreg16, segment reg
MOV mem16, segment reg
MOV segment reg, mreg16
MOV segment reg, mem16
MOVSB mem8,mem8
MOVSD mem16, mem16
MOVSW mem32, mem32
MUL AL, mreg8
MUL AL, mem8
MUL AX, mreg16
MUL AX, mem16
MUL EAX, mreg32
Table 29. VectorPath Integer Instructions (Continued)
Instruction Mnemonic