User's Manual

Use 8-Bit Sign-Extended Displacements 39
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Use 8-Bit Sign-Extended Displacements
Use 8-bit sign-extended displacements for conditional
branches. Using short, 8-bit sign-extended displacements for
conditional branches improves code density with no negative
effects on the AMD Athlon processor.
Code Padding Using Neutral Code Fillers
Occasionally a need arises to insert neutral code fillers into the
code stream, e.g., for code alignment purposes or to space out
branches. Since this filler code can be executed, it should take
up as few execution resources as possible, not diminish decode
density, and not modify any processor state other than
advancing EIP. A one byte padding can easily be achieved using
the NOP instructions (XCHG EAX, EAX; opcode 0x90). In the
x86 architecture, there are several multi-byte "NOP"
instructions available that do not change processor state other
than EIP:
■ MOV REG, REG
■ XCHG REG, REG
■ CMOVcc REG, REG
■ SHR REG, 0
■ SAR REG, 0
■ SHL REG, 0
■ SHRD REG, REG, 0
■ SHLD REG, REG, 0
■ LEA REG, [REG]
■ LEA REG, [REG+00]
■ LEA REG, [REG*1+00]
■ LEA REG, [REG+00000000]
■ LEA REG, [REG*1+00000000]
Not all of these instructions are equally suitable for purposes of
code padding. For example, SHLD/SHRD are microcoded which
reduces decode bandwidth and takes up execution resources.