Specifications

Product Errata 55
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
25759 Rev. 3.79 July 2009
94 Sequential Prefetch Feature May Cause Incorrect Processor
Operation
Description
On an instruction cache miss, the sequential prefetch mechanism may enable the early prefetch of the
next sequential cache line. Under a highly specific set of internal pipeline conditions this mechanism
may cause the processor to hang or execute incorrect code in 64-bit systems running 32-bit
compatibility mode applications.
Potential Effect on System
Processor may deadlock or execute incorrect code.
Suggested Workaround
BIOS should disable IC sequential prefetch for any system software which intends to operate in Long
Mode, by setting IC_CFG.DIS_SEQ_PREFETCH (bit 11 of MSR C001_1021). System software
should notify the BIOS what the expected operating mode is by using the Detect Target Operating
Mode callback (INT 15, function EC00h) as described in the BIOS and Kernel Developer’s Guide for
AMD Athlon™ 64 and AMD Opteron™ Processors, order# 26094.
Fix Planned
Yes