Am186ER and Am188ER Microcontrollers T F User’s Manual D R A
© 1997 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. (“AMD”) reserves the right to make changes in its products without notice in order to improve design or performance characteristics.
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TABLE OF CONTENTS PREFACE INTRODUCTION AND OVERVIEW Design Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User’s Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi CHAPTER 5 CHIP SELECT UNIT 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Chip Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 Ready and Wait-State Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 Chip Select Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.5 Chip Select Registers . . . . . . . . .
8.2 8.3 8.4 CHAPTER 9 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . .
viii CHAPTER 10 DMA CONTROLLER 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3 Programmable DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh) . . . . . . . . . . . . . . . . 10-3 10.3.
LIST OF FIGURES Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 6-1 Figure 7-1 Figure 7-2 Figure 7-3 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figur
Figure 8-25 Figure 8-26 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 12-1 Figure 12-2 Figure 12-3 Figure 12-4 Figure 12-5 Figure 12-6 Figure 13-1 Figure 13-2 Figure 13-3 Figure 13-4 Figure 13-5 Figure 13-6 Figure 13-7 Figure A-1 x Specific End-of-Interrupt Register (EOI, offset 22h). . . . . . . . . . . . . . . . . . . . .
LIST OF TABLES Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 4-1 Table 4-2 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 9-1 Table 10-1 Table 10-2 Table 10-3 Table 11-1 Table 11-2 Table 11-3 Table 12-1 Table 12-2 Table 13-1 Table 13-2 Table A-1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii Table of Contents
PREFACE INTRODUCTION AND OVERVIEW DESIGN PHILOSOPHY AMD’s Am186™ and Am188Q™ family of microcontrollers is based on the architecture of the original 8086 and 8088 microcontrollers, and currently includes the 80C186, 80C188, 80L186, 80L188, Am186ER, Am188ER, Am186EMLV, Am188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV, Am186EM, Am188EM, Am186ED, and Am186EDLV microcontrollers.
n Chapter 4 provides a description of the peripheral control block along with power management and reset configuration. n Chapter 5 provides a description of the chip select unit. n Chapter 6 provides a description of the internal memory. n Chapter 7 provides a description of the refresh control unit. n Chapter 8 provides a description of the on-chip interrupt controller. n Chapter 9 describes the timer control unit. n Chapter 10 describes the DMA controller.
CHAPTER 1 FEATURES AND PERFORMANCE Compared to the 80C186/188 microcontrollers, the Am186™ER and Am188™ER microcontrollers enable designers to increase performance and functionality, while reducing the cost, size, and power consumption of embedded systems. The Am186ER and Am188ER microcontrollers are cost-effective, enhanced versions of the AMD 80C186/188 devices.
The Am186ER and Am188ER microcontrollers are part of the AMD E86 family of embedded microcontrollers and microprocessors based on the x86 architecture. The 16-bit members of the E86 family, referred to throughout this manual as the Am186 and Am188 family, include the 80C186, 80C188, 80L186, 80L188, Am186ER, Am188ER, Am186EM, Am188EM, Am186EMLV, Am188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV, Am186ED and Am186EDLV microcontrollers.
n Familiar 80C186 peripherals: – Two independent DMA channels – Programmable interrupt controller with six external interrupts – Three programmable 16-bit timers – Programmable memory and peripheral chip-select logic – Programmable wait-state generator – Power-save clock divider n Software-compatible with the 80C186/188 microcontroller n Widely available native development tools, applications, and system software n Available for commercial or industrial temperature range n Available in the following package
Figure 1-1 Am186ER Microcontroller Block Diagram INT2/INTA0 INT3/INTA1/IRQ CLKOUTA INT1/SELECT INT4 TMROUT0 INT0 CLKOUTB TMRIN0 NMI X2 X1 VCC Clock and Power Management Unit Interrupt Control Unit Execution Unit GND Control Registers TMRIN1 Timer Control Unit 0 1 (WDT) Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers DRQ0 DRQ1 DMA Unit 2 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
Figure 1-2 Am188ER Microcontroller Block Diagram INT2/INTA0 INT3/INTA1/IRQ CLKOUTA INT1/SELECT INT4 TMROUT0 INT0 CLKOUTB TMRIN0 NMI X2 X1 VCC Clock and Power Management Unit Interrupt Control Unit Execution Unit GND Control Registers TMRIN1 DRQ0 DRQ1 DMA Unit Timer Control Unit 0 1 (WDT) 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
1.3 APPLICATION CONSIDERATIONS The integration enhancements of the Am186ER and Am188ER microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The internal 32-Kbyte RAM allows the manufacture of a complete embedded system using only one external ROM device and a low-cost crystal, plus any voltage conversion or current drivers required for I/O.
1.3.2 Memory Interface The integrated memory controller logic of the Am186ER and Am188ER microcontrollers provides a direct address bus interface to memory devices. The use of an external address latch controlled by the address latch enable (ALE) signal is not required. Individual byte write-enable signals are provided to eliminate the need for external high/ low-byte, write-enable circuitry.
1.4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS The FusionE86 Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-to-market needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
CHAPTER 2 PROGRAMMING All members of the Am186 and Am188 family of microcontrollers, including the Am186ER and Am188ER, contain the same basic set of registers, instructions, and addressing modes, and are compatible with the original industry-standard 186/188 parts. 2.1 REGISTER SET The base architecture of the Am186ER and Am188ER microcontrollers has 14 registers, as shown in Figure 2-1.
Figure 2-1 Register Set 16-Bit Register Name Byte Addressable (8-Bit Register Names Shown) 7 0 7 0 Special Register Functions 16-Bit Register Name 15 CS Code Segment DS Data Segment SS Stack Segment AX AH AL DX DH DL Multiply/Divide I/O Instructions CX CH CL Loop/Shift/Repeat/Count BX BH BL BP Base Pointer SI Source Index DI Destination Index Segment Registers 15 Index Registers SP 0 General Registers 2.1.
Bit 9: Interrupt-Enable Flag (IF)—When set, enables maskable interrupts to cause the CPU to transfer control to a location specified by an interrupt vector. Bit 8: Trace Flag (TF)—When set, a trace interrupt occurs after instructions execute. TF is cleared by the trace interrupt after the processor status flags are pushed onto the stack. The trace service routine can continue tracing by popping the flags back with an interrupt return (IRET) instruction.
Figure 2-3 Physical Address Generation Shift Left 4 Bits 1 2 A 4 19 1 15 2 A 0 15 0 2 4 Segment Logical 0 Base Address 2 Offset 0 0 0 0 0 15 0 1 2 A 2 6 19 2 0 2 Physical Address 0 To Memory 2.3 I/O SPACE The I/O space consists of 64K 8-bit or 32K 16-bit ports. The IN and OUT instructions address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX Register.
Table 2-1 Instruction Set Mnemonic Instruction Name AAA ASCII adjust for addition AAD ASCII adjust for division AAM ASCII adjust for multiplication AAS ASCII adjust for subtraction ADC Add byte or word with carry ADD Add byte or word AND Logical AND byte or word BOUND Detects values outside prescribed range CALL Call procedure CBW Convert byte to word CLC Clear carry flag CLD Clear direction flag CLI Clear interrupt-enable flag CMC Complement carry flag CMP Compare byte or wo
2-6 Mnemonic Instruction Name JB/JNAE Jump if below/not above or equal JBE/JNA Jump if below or equal/not above JC Jump if carry JCXZ Jump if register CX = 0 JE/JZ Jump if equal/zero JG/JNLE Jump if greater/not less or equal JGE/JNL Jump if greater or equal/not less JL/JNGE Jump if less/not greater or equal JLE/JNG Jump if less or equal/not greater JMP Jump JNC Jump if not carry JNE/JNZ Jump if not equal/not zero JNO Jump if not overflow JNP/JPO Jump if not parity/parity odd J
Mnemonic Instruction Name OR Logical inclusive OR byte or word OUT Output byte or word POP Pop word off stack POPA Pop all general register off stack POPF Pop flags off stack PUSH Push word onto stack PUSHA Push all general registers onto stack PUSHF Push flags onto stack RCL Rotate left through carry byte or word RCR Rotate right through carry byte or word REP Repeat REPE/REPZ Repeat while equal/zero REPNE/ REPNZ Repeat while not equal/not zero RET0 Return from procedure ROL
2.5 SEGMENTS The Am186ER and Am188ER microcontrollers use four segment registers: 1. Data Segment (DS): The processor assumes that all accesses to the program’s variables are from the 64K space pointed to by the DS Register. The data segment holds data, operands, etc. 2. Code Segment (CS): This 64K space is the default location for all instructions. All code must be executed from the code segment. 3.
n String—A contiguous sequence of bytes or words. A string can contain from 1 byte up to 64 Kbyte. n Pointer—A 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component plus a 16-bit offset component. In general, individual data elements must fit within defined segment limits. Figure 2-5 graphically represents the data types supported by the Am186ER and Am188ER microcontrollers.
2.7 ADDRESSING MODES The Am186ER and Am188ER microcontrollers use eight categories of addressing modes to specify operands. Two addressing modes are provided for instructions that operate on register or immediate operands; six modes are provided to specify the location of an operand in a memory segment. Register and Immediate Operands n Register Operand Mode—The operand is located in one of the 8- or 16-bit registers. n Immediate Operand Mode—The operand is included in the instruction.
CHAPTER 3 SYSTEM OVERVIEW This chapter contains descriptions of the Am186ER and Am188ER microcontroller pins, the bus interface unit, the clock and power management unit, and the power-save operation. 3.1 PIN DESCRIPTIONS Pin Terminology The following terms are used to describe the pins: Input—An input-only pin. Output—An output-only pin. Input/Output—A pin that can be either input or output. Synchronous—Synchronous inputs must meet setup and hold times in relation to CLKOUTA.
The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is not asserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state.
AO8 and AD7–AD0 for the Am188ER microcontroller). The address is guaranteed to be valid on the trailing edge of ALE. This pin is threestated during ONCE mode. ARDY Asynchronous Ready (input, asynchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. The falling edge of ARDY must be synchronized to CLKOUTA.
functionality in this instance. See Table 3-1 on page 3-10.) The pin is sampled within three crystal clock cycles after the rising edge of RES. BHE/ADEN is three-stated during bus holds and ONCE mode. See section 5.5.1 and section 5.5.2 for additional information on enabling and disabling the AD bus during the address phase of a bus cycle. CLKOUTA Clock Output A (output, synchronous) This pin supplies the internal clock to the system.
When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (e.g., for refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus.
INT2/INTA0 Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) INT2—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edgetriggered or level-triggered.
LCS/ONCE0 Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS—This pin indicates to the system that a memory access is in progress to the lower memory block. The size of the lower memory block is programmable up to 512 Kbyte. LCS is held High during a bus hold condition. ONCE0—During reset, this pin and UCS/ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES.
executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine (via the STI instruction for example), the fact that an NMI is currently in service will not have any effect on the priority resolution of maskable interrupt requests.
Note: Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the original 80C186 and 80C188 microcontrollers. A2—When the EX bit in the MCS and PCS Auxiliary Register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value.
Table 3-1 PIO Pin Assignments—Numeric Listing PIO No.
Table 3-2 PIO Pin Assignments—Alphabetic Listing Associated Pin PIO No.
RD Read Strobe (output, synchronous, three-state) RD—This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed not to be asserted before the address and data bus is three-stated during the address-to-data transition. RD is three-stated during bus holds and ONCE mode. RES Reset (input, asynchronous, level-sensitive) This pin causes the microcontroller to perform a reset.
S2 Bus Cycle Status (output, three-state, synchronous) S2—This pin indicates to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/O indicator. S2–S0 are three-stated during bus holds, hold acknowledges, and ONCE mode. During reset, these pins are pullups. The S2–S0 pins are encoded as shown in Table 3-3.
If CLKSEL1 is held Low during power-on reset, the chip enters the Divide by Two clocking mode where the fundamental clock is derived by dividing the external clock input by two. If Divide by Two mode is selected, the PLL is disabled. See Table 3-4, “Clocking Modes,” on page 3-16. This pin is latched within three crystal clock cycles after the rising edge of RES. Note that clock selection must be stable four clock cycles prior to exiting reset (i.e., RES going High).
TMRIN1 Timer Input 1 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used. TMROUT0 Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle.
If CLKSEL2 is held Low during power-on reset, the processor enters Times One mode. See Table 3-4. This pin is latched within three crystal clock cycles after the rising edge of RES. Note that clock selection must be stable four clock cycles prior to exiting reset (i.e., RES going High). UZI/CLKSEL2 is three-stated during bus holds and ONCE mode.
WR Write Strobe (output, synchronous) WR—This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR is three-stated during a bus hold or reset condition. X1 Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode crystal used by the internal oscillator circuit. If providing an external clock source, connect the source to X1 and ground X2.
3.2 BUS OPERATION The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186ER and Am188ER microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1–t4).
Figure 3-1 Am186ER Microcontroller Address Bus—Normal Read and Write Operation t1 t2 t3 Address Phase t4 Data Phase CLKOUTA A19–A0 Address AD15–AD0 (Read) Address AD15–AD0 (Write) Address Data Data LCS or UCS MCSx, PCSx Figure 3-2 Am186ER Microcontroller—Read and Write with Address Bus Disable In Effect t1 Address Phase t2 t3 Data Phase t4 CLKOUTA A19–A0 Address AD7–AD0 (Read) Data AD15–AD8 (Read) Data AD15–AD0 (Write) Data LCS, UCS System Overview 3-19
Figure 3-3 Am188ER Microcontroller Address Bus—Normal Read and Write Operation t1 t2 t3 Address Phase t4 Data Phase CLKOUTA A19–A0 AD7–AD0 (Read) Address Address Data AO15–AO8 (Read or Write) AD7–AD0 (Write) Address Address Data LCS or UCS MCSx, PCSx Figure 3-4 Am188ER Microcontroller—Read and Write with Address Bus Disable In Effect t1 t2 Address Phase t3 t4 Data Phase CLKOUTA A19–A0 Address AD7–AD0 (Read) Data AO15–AO8 Address AD7–AD0 (Write) Data LCS, UCS 3-20 System Ov
3.3 BUS INTERFACE UNIT The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the peripheral control block.
The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the Clock Prescaler (CDRAM) Register must be configured with the required refresh interval value. The ending address of LCS space and the ready and waitstate generation in the LMCS Register must also be programmed. The refresh counter reload value in the CDRAM Register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh.
3.4 CLOCK AND POWER MANAGEMENT UNIT The clock and power management unit of the Am186ER and Am188ER microcontrollers includes a phase-locked loop (PLL) and a second programmable system clock output (CLKOUTB). 3.4.1 Phase-Locked Loop (PLL) In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal clock.
3.4.2 Crystal-Driven Clock Source The internal oscillator circuit of the microcontroller is designed to function with a parallel resonant fundamental crystal. Because of the PLL, the crystal frequency can be twice, equal to, or one quarter of the processor frequency. Do not replace a crystal with an LC or RC equivalent. The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (Figure 3-5).
3.4.4 System Clocks Figure 3-6 shows the organization of the clocks. The 80C186 microcontroller system clock has been renamed CLKOUTA. CLKOUTB is provided as an additional output. Figure 3-6 Clock Organization PSEN1 Power-Save Divisor1 (/1 to /128) CLKSEL2 CAF1 CAD1 Mux PLL 1x or 4x CPU Clock Mux CLKOUTA Mux X1, X2 Input Clock Fundamental Clock CBF1 ÷2 Mux CLKSEL1 CBD1 Time Delay 6 ± 2.5ns CLKOUTB Notes: 1.
3-26 System Overview
CHAPTER 4 4.1 PERIPHERAL CONTROL BLOCK OVERVIEW The Am186ER and Am188ER microcontroller integrated peripherals are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte control block—the peripheral control block (PCB). Registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Figure 4-1 shows a map of the peripheral control block registers.
Figure 4-1 Peripheral Control Block Register Map Offset (Hexadecimal) Register Name FE Peripheral Control Block Relocation Register w w F6 Reset Configuration Register F4 Processor Release Level Register F0 PDCON Register w w E4 Enable RCU Register E2 Clock Prescaler Register E0 w DA DMA 1 Control Register D8 DMA 1 Transfer Count Register D6 DMA 1 Destination Address High Register D4 DMA 1 Destination Address Low Register D2 DMA 1 Source Address High Register D0 DMA 1 Source A
Offset (Hexadecimal) w Register Name 7A PIO Data 1 Register 78 PIO Direction 1 Register 76 74 PIO Mode 1 Register PIO Data 0 Register 72 PIO Direction 0 Register w w 66 Timer 2 Mode/Control Register 62 Timer 2 Maxcount Compare A Register Timer 2 Count Register 60 5E Timer 1 Mode/Control Register 5C Timer 1 Maxcount Compare B Register Timer 1 Maxcount Compare A Register 5A 58 Timer 0 Mode/Control Register Timer 0 Maxcount Compare B Register 50 Timer 0 Count Register Timer 0 Maxcount C
4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh) The peripheral control block is mapped into either memory or I/O space by programming the Peripheral Control Block Relocation (RELREG) Register (see Figure 4-2). This register is a 16-bit register at offset FEh from the control block base address. The RELREG Register provides the upper 12 bits of the base address of the control block. The control block is effectively an internal chip select range.
4.1.2 Reset Configuration Register (RESCON, Offset F6h) The Reset Configuration (RESCON) Register (see Figure 4-3) in the peripheral control block latches system-configuration information that is presented to the processor on the address/data bus (AD15–AD0 for the Am186ER or AO15–AO8 and AD7–AD1 for the Am188ER) during the rising edge of reset. The interpretation of this information is system specific.
4.1.3 Processor Release Level Register (PRL, Offset F4h) The Processor Release Level (PRL) Register (Figure 4-4) is a read-only register that specifies the processor version. The format of the Processor Release Level Register is shown in Figure 4-4. Figure 4-4 Processor Release Level Register (PRL, offset F4h) 7 15 0 Reserved PRL 186/188 The values of the PRL Register bits 15–8 are listed in Table 4-1.
4.1.4 Power-Save Control Register (PDCON, Offset F0h) Figure 4-5 Power-Save Control Register (PDCON, offset F0h) 7 15 0 0 0 PSEN 0 0 0 0 0 0 CBF CAF CBD CAD F1 F2 F0 The value of the PDCON Register is 0000h at reset. Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables Power-Save mode and divides the internal operating clock by the value in F2–F0. PSEN is automatically cleared when an external interrupt occurs, including those generated by on-chip peripheral devices.
Bits 2–0: Clock Divisor Select (F2–F0)—Controls the division factor when Power-Save mode is enabled. Allowable values are as follows: 4.2 F2 0 F1 0 F0 0 Divider Factor Divide by 1 (20) 0 0 1 Divide by 2 (21) 0 1 0 Divide by 4 (22) 0 1 1 Divide by 8 (23) 1 0 0 Divide by 16 (24) 1 0 1 Divide by 32 (25) 1 1 0 Divide by 64 (26) 1 1 1 Divide by 128 (27) INITIALIZATION AND PROCESSOR RESET Processor initialization or startup is accomplished by driving the RES input pin Low.
Table 4-2 Initial Register State After Reset Register Name Mnemonic Value at Reset Processor Status Flags F F002h Instruction Pointer IP 0000h Comments Interrupts disabled Code Segment CS FFFFh Boot address is FFFF0h Data Segment DS 0000h DS = ES = SS = 0000h Extra Segment ES 0000h Stack Segment SS 0000h Processor Release Level PRL XXxxh PRL XX = Revision (lower half-word is undefined) Peripheral Control Block Relocation Memory Partition RELREG 20FFh MDRAM 0000h Peripheral
4-10 Peripheral Control Block
CHAPTER 5 CHIP SELECT UNIT 5.1 OVERVIEW The Am186ER and Am188ER microcontrollers contain logic that provides programmable chip select generation for both memories and peripherals. In addition, the logic can be programmed to provide ready or wait-state generation and latched address bits A1 and A2. The chip select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit.
Except for the UCS chip select, which is active on reset as discussed in section 5.5.1, external memory chip selects are not activated until the associated registers have been accessed by a write operation. The LCS chip select is activated when the LMCS Register is written, the MCS chip selects are activated after both the MMCS and MPCS registers have been written, and the PCS chip selects are activated after both the PACS and MPCS registers have been written. 5.
When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS Register will disable the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. The MCS and PCS chip select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs.
5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) The Am186ER and Am188ER microcontrollers provide the UCS chip select pin for the top of memory. On reset, the microcontroller begins fetching and executing instructions starting at memory location FFFF0h, so upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset with a default memory range of 64 Kbyte from F0000h to FFFFFh, external ready required, and three wait states automatically inserted.
Bits 11–8: Reserved Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during the address phase of a bus cycle when UCS is asserted. If DA is set to 1, AD15–AD0 is not driven during the address phase of a bus cycle when UCS is asserted. If DA is set to 0, AD15–AD0 is driven during the address phase of a bus cycle. Disabling AD15–AD0 reduces power consumption. DA defaults to 0 at power-on reset.
5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) The Am186ER and Am188ER microcontrollers provide the LCS chip select pin for the bottom of memory. Because the interrupt vector table is located at 00000h at the bottom of memory, the LCS pin has been provided to facilitate this usage. The LCS pin is not active on reset, but any write access to the LMCS Register activates this pin. The Low Memory Chip Select is configured through the LMCS Register (see Figure 5-2).
Bits 11–8: Reserved—Set to 1. Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during the address phase of a bus cycle when LCS is asserted. If DA is set to 1, AD15–AD0 is not driven during the address phase of a bus cycle when LCS is asserted. If DA is set to 0, AD15–AD0 is driven during the address phase of a bus cycle. Disabling AD15–AD0 reduces power consumption.
5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) The Am186ER and Am188ER microcontrollers provide four chip select pins, MCS3–MCS0, for use within a user-locatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS and LCS chip selects (and, if they are mapped to memory, the address range of the Peripheral Chip Selects, PCS6–PCS5 and PCS3–PCS0).
be active in this case. Use of the MCS chip selects to access low memory allows the timing of these accesses to follow the AD address bus rather than the A address bus. Locating a 512K MMCS block at 80000h always conflicts with the range of the UCS chip select and is not allowed. Bits 8–3: Reserved—Set to 1. Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the MCS chip selects. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is ignored.
5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) The PCS and MCS Auxiliary (MPCS) Register (see Figure 5-4) differs from the other chip select control registers in that it contains fields that pertain to more than one type of chip select. The MPCS Register fields provide program information for MCS3–MCS0 as well as PCS6–PCS5 and PCS3–PCS0.
Bit 7: Pin Selector (EX)—This bit determines whether the PCS6–PCS5 pins are configured as chip selects or as alternate outputs for A2–A1. When this bit is set to 1, PCS6–PCS5 are configured as peripheral chip select pins. When EX is set to 0, PCS5 becomes address bit A1 and PCS6 becomes address bit A2. Bit 6: Memory/ I/O Space Selector (MS)—This bit determines whether the PCS pins are active during memory bus cycles or I/O bus cycles. When MS is set to 1, the PCS outputs are active for memory bus cycles.
5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) Unlike the UCS and LCS chip selects, the PCS outputs assert with the same timing as the multiplexed AD address bus. Also, each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. The Am186ER and Am188ER microcontrollers provide six chip selects, PCS6–PCS5 and PCS3–PCS0, for use within a user-locatable memory or I/O block.
microcontroller in which bit 6 was set with a meaningful value would not produce the address expected on the Am186ER. When the PCS chip selects are mapped to I/O space, BA19–16 must be programmed to 0000b because the I/O address bus is only 16-bits wide.
5-14 Chip Select Unit
CHAPTER 6 6.1 INTERNAL MEMORY OVERVIEW The Am186ER and Am188ER microcontrollers provide 32 Kbyte of on-chip RAM. The integration of memory helps reduce a system design’s overall cost, size, and power consumption. The internal RAM for the Am186ER microcontroller is a 16K x 16-bit-wide array, which provides the same performance as 16-bit external zero-wait-state RAM.
6.3 EMULATOR AND DEBUG MODES There are two debug modes associated with the internal memory. One mode allows users to disable the internal RAM, and the other mode makes it possible to drive data on the external data bus during internal RAM read cycles. Normal operation of internal RAM has all control signals for reads and writes and data for writes visible externally. Accesses to internal memory can be detected externally by comparing the address on A19–A0 with the address space of the internal memory. 6.
6.4 INTERNAL MEMORY CHIP SELECT REGISTER (IMCS, OFFSET ACh) The Internal Memory Chip Select (IMCS) Register provides programmable chip select generation for the internal RAM. It allows the base address of the internal memory space to be placed on any 32-Kbyte boundary. The register also contains a control bit to enable the internal memory and another to enable data read from the internal memory to be driven on the external data bus.
6-4 Internal Memory
CHAPTER 7 7.1 REFRESH CONTROL UNIT OVERVIEW The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. The Refresh Control Unit operates off the processor internal clock. If the Power-Save mode is in effect, the Refresh Control Unit must be reprogrammed to reflect the new clock rate.
7.1.2 Clock Prescaler Register (CDRAM, Offset E2h) Figure 7-2 Clock Prescaler Register (CDRAM, offset E2h) 7 15 0 0 0 0 0 0 0 0 RC8–RC0 The CDRAM Register is undefined on reset. Bits 15–9: Reserved—Read back as 0. Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired clock count interval between refresh cycles. The counter value should not be set to less than 18 (12h), otherwise there would never be sufficient bus cycles available for the processor to execute code.
CHAPTER 8 8.1 INTERRUPT CONTROL UNIT OVERVIEW The Am186ER and Am188ER microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are six external interrupt sources on the Am186ER and Am188ER microcontrollers— five maskable interrupt pins (INT4–INT0) and the nonmaskable interrupt (NMI) pin.
The processor calculates the index to the interrupt vector table by shifting the interrupt type left 2 bits (multiplying by 4). 8.1.1.3 Maskable and Nonmaskable Interrupts Interrupt types 08h through 1Fh are maskable. Of these, only 08h through 14h are actually in use (see Table 8-1). The maskable interrupts are enabled and disabled by the interrupt enable flag (IF) in the processor status flags, but the INT command can execute any interrupt regardless of the setting of IF.
8.1.1.8 Software Exceptions A software exception interrupt occurs when an instruction causes an interrupt due to some condition in the processor. Interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are software exception interrupts. Software exceptions are not maskable and are not affected by the setting of the IF flag.
8.1.2 Interrupt Conditions and Sequence Interrupts are generally serviced as follows. 8.1.2.1 Nonmaskable Interrupts Nonmaskable interrupts—the trace interrupt, the NMI interrupt, and software interrupts (including both user-defined INT statements and software exceptions)—are serviced regardless of the setting of the interrupt enable flag (IF) in the processor status flags. 8.1.2.
8.1.3 Interrupt Priority Table 8-1 shows the predefined types and overall priority structure for the Am186ER and Am188ER microcontrollers. Nonmaskable interrupts (interrupt types 0–7) are always higher priority than maskable interrupts. Maskable interrupts have a programmable priority that can override the default priorities relative to one another.
8.1.4 Software Exceptions, Traps, and NMI The following predefined interrupts cannot be masked by programming. 8.1.4.1 Divide Error Exception (Interrupt Type 00h) Generated when a DIV or IDIV instruction quotient cannot be expressed in the number of destination bits. 8.1.4.2 Trace Interrupt (Interrupt Type 01h) If the trace flag (TF) in the Processor Status Flags Register is set, the trace interrupt is generated after most instructions. This interrupt allows programs to execute in single-step mode.
8.1.4.4 Breakpoint Interrupt (Interrupt Type 03h) An interrupt caused by the 1-byte version of the INT instruction (INT3). 8.1.4.5 INTO Detected Overflow Exception (Interrupt Type 04h) Generated by an INTO instruction if the OF bit is set in the Processor Status Flags (FLAGS) Register. 8.1.4.6 Array BOUNDS Exception (Interrupt Type 05h) Generated by a BOUND instruction if the array index is outside the array bounds.
8.1.5 Interrupt Acknowledge Interrupts can be acknowledged in two different ways—the internal interrupt controller can provide the interrupt type or an external interrupt controller can provide the interrupt type. The processor requires the interrupt type as an index into the interrupt vector table. When the internal interrupt controller is supplying the interrupt type and INT0 or INT1 is programmed in Cascade mode, no interrupt acknowledge bus cycles are generated.
8.1.6 Interrupt Controller Reset Conditions On reset, the interrupt controller performs the following nine actions: 1. All special fully nested mode (SFNM) bits are reset, implying fully nested mode. 2. All priority (PR) bits in the various control registers are set to 1. This places all sources at the lowest priority (level 7). 3. All level-triggered mode (LTM) bits are reset to 0, resulting in edge-triggered mode. 4. All interrupt in-service bits are reset to 0. 5.
8.2 MASTER MODE OPERATION This section describes Master mode operation of the internal interrupt controller. See section 8.4 on page 8-29 for a description of Slave mode operation. Six pins are provided for external interrupt sources. One of these pins is NMI, the nonmaskable interrupt. NMI is generally used for unusual events like power failure.
8.2.2 Cascade Mode The Am186ER and Am188ER microcontrollers have five interrupt pins, two of which (INT2 and INT3) have dual functions. In fully nested mode, the five pins are used as direct interrupt inputs and the corresponding interrupt types are generated internally. In Cascade mode, four of the five pins can be configured into interrupt input and dedicated acknowledge signal pairs. INT0 can be configured with interrupt acknowledge INTA0 (INT2).
8.2.3 Special Fully Nested Mode Special fully nested mode is entered by setting the SFNM bit in the INT0 or INT1 control registers. (See section 8.3.1 on page 8-14.) It enables complete nesting with external 82C59A masters or multiple interrupts from the same external interrupt pin when not in Cascade mode. In this case, the ISRs must be re-entrant. In fully nested mode, an interrupt request from an interrupt source is not recognized when the in-service bit for that source is set.
8.3 MASTER MODE INTERRUPT CONTROLLER REGISTERS The interrupt controller registers for Master mode are shown in Table 8-2. All the registers can be read and written unless otherwise specified. Registers can be redefined in Slave mode. See section 8.4 on page 8-29 for detailed information regarding Slave mode register usage. On reset, the microcontroller is in Master mode. Bit 14 of the Relocation Register (see Figure 4-2) must be set to initiate Slave mode operation.
8.3.1 INT0 and INT1 Control Registers (I0CON, Offset 38h, I1CON, Offset 3Ah) (Master Mode) The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to interrupt type 0Dh. When Cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin becomes INTA0, the interrupt acknowledge for INT0. When Cascade mode is enabled for INT1 by setting the C bit of I1CON to 1, the INT3 pin becomes INTA1, the interrupt acknowledge for INT1.
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT0 or INT1 relative to the other interrupt signals, as shown in Table 8-3, “Priority Level,” on page 8-15.
8.3.2 INT2 and INT3 Control Registers (I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode) The INT2 interrupt is assigned to interrupt type OEh. The INT3 interrupt is assigned to interrupt type 0Fh. The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA0 and INTA1 when Cascade mode is implemented. Figure 8-5 INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh) 7 15 0 Reserved MSK PR1 LTM PR2 PR0 The value of I2CON and I3CON at reset is 000Fh.
8.3.3 INT4 Control Register (I4CON, Offset 40h) (Master Mode) The Am186ER and Am188ER microcontrollers provide INT4, an additional external interrupt pin. This input behaves like INT3–INT0 on the 80C186/188 microcontroller with the exception that INT4 is only intended for use as a nested-mode interrupt source. This interrupt is assigned to interrupt type 10h. The Interrupt 4 Control Register (see Figure 8-6) controls the operation of the INT4 signal.
8.3.4 Timer and DMA Interrupt Control Registers (TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON, Offset 36h) (Master Mode) The three timer interrupts are assigned to interrupt types 08h, 12h, and 13h. All three timer interrupts are configured through TCUCON, offset 32h. The DMA0 interrupt is assigned to interrupt type 0Ah. The DMA1 interrupt is assigned to interrupt type 0Bh. See Chapter 10, “DMA Controller,” for information about using these pins for DMA requests.
8.3.5 Watchdog Timer Interrupt Control Register (WDCON, Offset 42h) (Master Mode) The watchdog timer is implemented by connecting the TMROUT1 output to an additional internal interrupt to create the watchdog timer interrupt. This interrupt is assigned to interrupt type 11h. The control register format is shown in Figure 8-8. The systems programmer should program the timer (see section 9.2.2 on page 9-3) and then program the interrupt control register.
8.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h) (Master Mode) The Serial Port Interrupt Control (SPICON) Register controls the operation of the asynchronous serial port interrupt source (SPI, bit 10 in the Interrupt Request Register). This interrupt is assigned to interrupt type 14h. The control register format is shown in Figure 8-9. Figure 8-9 Serial Port Interrupt Control Register (SPICON, offset 44h) 7 15 Reserved 0 1 MSK PR1 Res PR2 PR0 The value of SPICON at reset is 001Fh.
8.3.7 Interrupt Status Register (INTSTS, Offset 30h) (Master Mode) The Interrupt Status (INTSTS) Register indicates the interrupt request status of the three timers. Figure 8-10 Interrupt Status Register (INTSTS, offset 30h) 7 15 0 Reserved DHLT TMR2 TMR0 TMR1 Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This bit is automatically set to 1 when nonmaskable interrupts occur and is reset when an IRET instruction is executed.
8.3.8 Interrupt Request Register (REQST, Offset 2Eh) (Master Mode) The hardware interrupt sources have interrupt request bits inside the interrupt controller. A read from this register yields the status of these bits. The Interrupt Request (REQST) Register is a read-only register. The format of the Interrupt Request Register is shown in Figure 8-11.
8.3.9 In-Service Register (INSERV, Offset 2Ch) (Master Mode) The bits in the In Service (INSERV) Register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared by writing the corresponding interrupt type to the End-of-Interrupt (EOI) Register. See Table 8-1, “Am186ER and Am188ER Microcontroller Interrupt Types,” on page 8-3.
8.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode) The Priority Mask (PRIMSK) Register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 8-13 Priority Mask Register (PRIMSK, offset 2Ah) 7 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRM2 PRM1 PRM0 The value of PRIMSK at reset is 0007h. Bits 15–3: Reserved—Set to 0.
8.3.11 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) The Interrupt Mask (IMASK) Register is a read/write register. Programming a bit in the IMASK Register has the effect of programming the MSK bit in the associated control register. The format of the IMASK Register is shown in Figure 8-14. Do not write to the Interrupt Mask Register while interrupts are enabled. To modify mask bits while interrupts are enabled, use the individual interrupt control registers.
8.3.12 Poll Status Register (POLLST, Offset 26h) (Master Mode) The Poll Status (POLLST) Register mirrors the current state of the Poll Register. The POLLST Register can be read without affecting the current interrupt request. But when the Poll Register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll Register.
8.3.13 Poll Register (POLL, Offset 24h) (Master Mode) When the Poll Register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll Register. The Poll Status Register mirrors the current state of the Poll Register, but the Poll Status Register can be read without affecting the current interrupt request. Figure 8-16 Poll Register (POLL, offset 24h) 7 15 Reserved 0 S4–S0 IREQ Bit 15: Interrupt Request (IREQ)—Set to 1 if an interrupt is pending.
8.3.14 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode) The End-of-Interrupt (EOI) Register is a write-only register. The in-service flags in the InService Register (see section 8.3.9 on page 8-23) are reset by writing to the EOI Register. Before executing the IRET instruction that ends an interrupt service routine (ISR), the ISR should write to the EOI Register to reset the IS bit for the interrupt. The specific EOI reset is the most secure method to use for resetting IS bits.
8.4 SLAVE MODE OPERATION When Slave mode is used, the microcontroller’s internal interrupt controller is used as a slave controller to an external master interrupt controller. The internal interrupts are monitored by the internal interrupt controller, while the external controller functions as the system master interrupt controller. On reset, the microcontroller is in Master mode. To activate Slave mode operation, bit 14 of the Relocation Register must be set (see Figure 4-2 on page 4-4).
8.4.3 Timer and DMA Interrupt Control Registers (T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h) (Slave Mode) In Slave mode, there are three separate registers for the three timers. In Master mode, all three timers are masked and prioritized in one register, TCUCON. In Slave mode, the two DMA control registers retain their functionality and addressing from Master mode.
8.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode) The Interrupt Status Register controls DMA activity when nonmaskable interrupts occur and indicates the current interrupt status of the three timers. Figure 8-20 Interrupt Status Register (INTSTS, offset 30h) 7 15 0 Reserved DHLT TMR1 TMR2 TMR0 The INTSTS Register is set to 0000h on reset. Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity.
8.4.5 Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode) The internal interrupt sources have interrupt request bits inside the interrupt controller. A read from this register yields the status of these bits. The Interrupt Request Register is a read-only register. The format of the Interrupt Request Register is shown in Figure 8-21. For internal interrupts (D1, D0, TMR2, TMR1, and TMR0), the corresponding bit is set to 1 when the device requests an interrupt.
8.4.6 In-Service Register (INSERV, Offset 2Ch) (Slave Mode) The format of the In-Service Register is shown in Figure 8-22. The bits in the In-Service Register are set by the interrupt controller when the interrupt is taken. The in-service bits are cleared by writing to the End-of-Interrupt (EOI) Register. Figure 8-22 In-Service Register (INSERV, offset 2Ch) 7 15 0 Reserved TMR2 D1 Res TMR1 D0 TMR0 The INSERV Register is set to 0000h on reset.
8.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode) The format of the Priority Mask Register is shown in Figure 8-23. The Priority Mask Register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 8-23 Priority Mask Register (PRIMSK, offset 2Ah) 7 15 0 Reserved PRM2 PRM1 PRM0 The value of the PRIMSK Register at reset is 0007h.
8.4.8 Interrupt Mask Register (IMASK, Offset 28h) (Slave Mode) The format of the Interrupt Mask Register is shown in Figure 8-24. The Interrupt Mask Register is a read/write register. Programming a bit in the Interrupt Mask Register has the effect of programming the MSK bit in the associated control register. Figure 8-24 Interrupt Mask Register (IMASK, offset 28h) 7 15 0 Reserved TMR2 D1 Res TMR1 D0 TMR0 The IMASK Register is set to 003Dh on reset.
8.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) (Slave Mode) In Slave mode, a write to the EOI Register resets an in-service bit of a specific priority. The user supplies a three-bit priority-level value that points to an in-service bit to be reset. The command is executed by writing the correct value in the Specific EOI Register at offset 22h. Figure 8-25 Specific End-of-Interrupt Register (EOI, offset 22h) 7 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2–L0 The EOI Register is undefined on reset.
8.4.10 Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode) Vector generation in Slave mode is exactly like that of an 8259A or 82C59A slave. The interrupt controller generates an 8-bit interrupt type that the CPU shifts left two bits (multiplies by four) to generate an offset into the interrupt vector table. Figure 8-26 Interrupt Vector Register (INTVEC, offset 20h) 7 15 0 0 0 0 0 0 0 0 0 T4–T0 0 0 0 The INTVEC Register is undefined on reset. Bits 15–8: Reserved—Read as 0.
8-38 Interrupt Control Unit
CHAPTER 9 9.1 TIMER CONTROL UNIT OVERVIEW There are three 16-bit programmable timers in the Am186ER and Am188ER microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). These two timers can be used to count or time external events, or they can be used to generate nonrepetitive or variable-duty-cycle waveforms. Timer 1 can also be configured as a watchdog timer.
Each timer also has a corresponding maximum-count register that defines the maximum value for the timer. When the timer reaches the maximum value, it resets to 0 during the same clock cycle. (The value in the timer-count register never equals the maximum-count register.) In addition, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values.
9.2.2 Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56h, T1CON, Offset 5Eh) These registers control the functionality of timer 0 and timer 1. See Figure 9-1. Figure 9-1 Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON, offsets 56h and 5Eh) 7 15 0 0 0 0 0 0 0 MC RTG P INH RIU EN INT ALT CONT EXT The value of T0CON and T1CON at reset is 0000h. Bit 15: Enable Bit (EN)—When set to 1, the timer is enabled. When set to 0, the timer is inhibited from counting.
Bit 2: External Clock Bit (EXT)—When set to 1, an external clock is used. When set to 0, the internal clock is used. When the internal clock is used, the timer input pin is available for use as a programmable I/O pin. Bit 1: Alternate Compare Bit (ALT)—When set to 1, the timer counts to maxcount compare A, then resets the count register to 0. Then the timer counts to maxcount compare B, resets the count register to zero, and starts over with maxcount compare A.
9.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) This register controls the functionality of timer 2. See Figure 9-2. Figure 9-2 Timer 2 Mode and Control Register (T2CON, offset 66h) 7 15 0 0 0 0 0 0 0 0 0 0 0 0 MC INH INT EN CONT The value of T2CON at reset is 0000h. Bit 15: Enable Bit (EN)—When EN is set to 1, the timer is enabled. When set to 0, the timer is inhibited from counting. This bit can only be written with the INH bit set at the same time.
9.2.4 Timer Count Registers (T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) These registers can be incremented by one every four internal processor clocks. Timer 0 and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external signals, or they can be prescaled by timer 2. See Figure 9-3. The count registers are compared to maximum count registers and various actions are triggered based on reaching a maximum count.
9.2.5 Timer Maxcount Compare Registers (T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) These registers serve as comparators for their associated count registers. Timer 0 and timer 1 each have two maximum count compare registers. See Figure 9-4. Timer 0 and timer 1 can be configured to count and compare to register A and then count and compare to register B.
9-8 Timer Control Unit
CHAPTER 10 10.1 DMA CONTROLLER OVERVIEW Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186ER and Am188ER microcontrollers provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-to-I/O). Two bus cycles (a minimum of eight clocks) are necessary for each data transfer.
Figure 10-1 DMA Unit Block Diagram 20-bit Adder/Subtractor Adder Control Logic Timer Request DRQ1 20 Request Selection Logic Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 DRQ0 DMA Control Logic Interrupt Request Channel Control Register 1 Channel Control Register 0 20 16 Internal Address/Data Bus 10.
10.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh) The DMA control registers (see Figure 10-2) determine the mode of operation for the DMA channels.
Bit 11: Source Decrement (SDEC)—When SDEC is set to 1, the source address is automatically decremented after each transfer. The address decrements by 1 or 2 depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment and decrement bits are set to the same value (00b or 11b). Bit 10: Source Increment (SINC)—When SINC is set to 1, the source address is automatically incremented after each transfer. The address increments by 1 or 2 depending on the byte/word bit (B/W, bit 0).
10.3.2 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC, Offset D8h) Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA Control register. However, if the TC bit in the DMA control word is set or if unsynchronized transfers are programmed, DMA activity terminates when the Transfer Count register reaches 0.
10.3.3 DMA Destination Address High Register (High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h) Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each register takes up two full 16-bit registers (the high register and the low register) in the peripheral control block. For each DMA channel to be used, all four registers must be initialized. These registers can be individually incremented or decremented after each transfer.
10.3.4 DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h) Figure 10-5 shows the DMA Destination Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Destination Address High register (see Figure 10-4) to produce a 20-bit destination address. Figure 10-5 DMA Destination Address Low Register (D0DSTL, D1DSTL, offsets C4h and D4h) 15 7 0 DDA15–DDA0 The value of D0DSTL and D1DSTL at reset is undefined.
10.3.5 DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h) Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each register takes up two full 16-bit registers (the high register and the low register) in the peripheral control block. For each DMA channel to be used, all four registers must be initialized. These registers can be individually incremented or decremented after each transfer.
10.3.6 DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0h, D1SRCL, Offset D0h) Figure 10-7 shows the DMA Source Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Source Address High register (see Figure 106) to produce a 20-bit source address. Figure 10-7 DMA Source Address Low Register (D0SRCL, D1SRCL, offsets C0h and D0h) 15 7 0 DSA15–DSA0 The value of D0SRCL and D1SRCL at reset is undefined.
10.4 DMA REQUESTS Data transfers can be either source or destination synchronized—either the source of the data or the destination of the data can request the data transfer. DMA transfers can also be unsynchronized (i.e., the transfer takes place continually until the correct number of transfers has occurred).
10.4.1 Synchronization Timing DRQ1 or DRQ0 must be deasserted before the end of the DMA transfer to prevent another DMA cycle from occurring. The timing for the required deassertion depends on whether the transfer is source-synchronized or destination-synchronized. 10.4.1.1 Source Synchronization Timing Figure 10-8 shows a typical source-synchronized DMA transfer. The DRQ signal must be deasserted at least four clocks before the end of the transfer (at T1 of the deposit phase).
Figure 10-9 Destination Synchronized DMA Transfers Fetch Cycle T1 T2 T3 Deposit Cycle T4 T1 T2 T3 T4 TI TI CLKOUT DRQ (First case) 1 DRQ (Second case) 2 Notes: 1. This destination-synchronized transfer is not followed immediately by another DMA transfer. 2. This destination-synchronized transfer is immediately followed by another DMA transfer because DRQ is not deasserted soon enough. 10.4.2 DMA Acknowledge No explicit DMA acknowledge signal is provided.
Each DMA register can be modified while the channel is operating. If the CHG bit is set to 0 when the control register is written, the ST bit of the control register will not be modified by the write. If multiple channel registers are modified, an internally LOCKed string transfer should be used to prevent a DMA transfer from occurring between updates to the channel registers. 10.4.5 DMA Channels on Reset On reset, the state of the DMA channels is as follows: n The ST bit for each channel is reset.
10-14 DMA Controller
CHAPTER 11 ASYNCHRONOUS SERIAL PORT 11.1 OVERVIEW The Am186ER and Am188ER microcontrollers provide an asynchronous serial port. The asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer.
11.2.1 Serial Port Control Register (SPCT, Offset 80h) The Serial Port Control register controls both the transmit and receive sections of the serial port. The format of the Serial Port Control register is shown in Figure 11-1. Figure 11-1 Serial Port Control Register (SPCT, offset 80h) 7 15 0 Reserved TXIE RXIE LOOP BRK BRKVAL PMODE RMODE RSIE TMODE STP WLGN The value of SPCT at reset is 0000h. Bits 15–12: Reserved—Set to 0.
Bits 6–5: Parity Mode (PMODE)—This field specifies how parity generation and checking are performed during transmission and reception, as shown in Table 11-2. Table 11-2 Parity Mode Bit Settings Parity None (No parity bit in frame) Odd (Odd number of 1s in frame) Even (Even number of 1s in frame) PMODE 0X 10 11 If parity checking and generation is selected, a parity bit is received or sent in addition to the specified number of data bits. The value of PMODE after power-on reset is 00b.
11.2.2 Serial Port Status Register (SPSTS, Offset 82h) The Serial Port Status register indicates the status of the transmit and receive sections of the serial port. The format of the Serial Port Status register is shown in Figure 11-2. Figure 11-2 Serial Port Status Register (SPSTS, offset 82h) 7 15 0 Reserved TEMT THRE RDR BRKI FER OER PER Bits 15–7: Reserved—Set to 0.
11.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) Software writes this register (Figure 11-4) with data to be transmitted on the serial port. The transmitter is double-buffered, and the transmit section copies data from the transmit data register to the transmit shift register (which is not accessible to software) before transmitting the data. Figure 11-3 Serial Port Transmit Data Register (SPTD, offset 84h) 7 15 Reserved 0 TDATA The value of SPTD at reset is undefined.
11.2.4 Serial Port Receive Data Register (SPRD, Offset 86h) This register (Figure 11-4) contains data received over the serial port. The receiver is double-buffered, and the receive section can be receiving a subsequent frame of data in the receive shift register (which is not accessible to software) while the receive data register is being read by software. Figure 11-4 Serial Port Receive Data Register (SPRD, offset 86h) 7 15 Reserved 0 RDATA The value of SPRD at reset is undefined.
11.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h) This register (Figure 11-5) specifies a clock divisor for the generation of the serial clock that controls the serial port. The serial clock rate is 16 times the baud rate of transmission or reception of data. The SPBAUD register specifies the number of internal processor cycles in one phase (half period) of the 16x serial clock.
11-8 Asynchronous Serial Port
CHAPTER 12 SYNCHRONOUS SERIAL INTERFACE 12.1 OVERVIEW The synchronous serial interface enables the Am186ER and Am188ER microcontrollers to communicate with application-specific integrated circuits (ASICs) that require programmability but are short on pins. The four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 20 Mbit/s with a 40-MHz CPU clock. Unlike the asynchronous serial port, the SSI operates in a master/slave configuration.
12.1.1 Four-Pin Interface The SDEN1–SDEN0 pins can be used to enable data transfer individually for as many as two peripheral devices. Transmit and receive operations are synchronized between the master (Am186ER or Am188ER microcontroller) and slave (peripheral) by means of the SCLK output. SCLK is derived from the processor internal clock divided by 2, 4, 8, or 16, as specified by the SSC register. SCLK is only driven during data transmit or receive operations. The inactive state of SCLK is High.
12.2.1 Synchronous Serial Status Register (SSS, Offset 10h) This read-only register indicates the state of the SSI port. The format of the Synchronous Serial Status register is shown in Figure 12-1. Figure 12-1 Synchronous Serial Status Register (SSS, offset 10h) 7 15 0 Reserved RE/TE DR/DT PB The value of the SSS register at reset is 0000h. Bits 15–3: Reserved—Set to 0.
12.2.2 Synchronous Serial Control Register (SSC, Offset 12h) This read/write register controls the operation of the SDEN0–SDEN1 outputs and the transfer rate of the SSI port. The SDEN0 and SDEN1 outputs are asserted when a 1 is written to the corresponding bit. However, in the case when both DE0 and DE1 are set, only SDEN0 will be asserted. The format of the Synchronous Serial Control register is shown in Figure 12-2.
12.2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h) Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) The Synchronous Serial Transmit 1 and 0 registers contain data to be transferred from the processor to the peripheral on a write operation. Only the least-significant 8 bits of the register are used. The format of SSD1 and SSD0 is shown in Figure 12-3.
12.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) The Synchronous Serial Receive (SSR) register contains the data transferred from the peripheral to the processor on a read operation. Only the least-significant 8 bits of the register are used. The format of the SSR register is shown in Figure 12-4. A receive data transmission is initiated by reading the SSR register while the port is not busy (PB bit in SSS register is 0) and one or both of the enable bits (DE1–DE0 in the SSC register) is set.
12.3 SSI PROGRAMMING The SSI interface allows for a variety of software and hardware protocols. n Signaling a read/write—In general, software uses the first write to the SSI to transmit an address or count to the peripheral. This value can include a read/write flag in the case where the device supports both reads and writes.
Figure 12-5 PB=0 DR/DT=0 Synchronous Serial Interface Multiple Write PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=0 DR/DT=0 SDEN SCLK SDATA Poll SSS for PB=0 Write to SSD Poll SSS for PB=0 Poll SSS for PB=0 Write to SSD Write to SSD Write to SSC bit DE=0 Write to SSC bit DE=1 Figure 12-6 PB=0 DR/DT=0 Synchronous Serial Interface Multiple Read PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=1 DR/DT=0 PB=0 DR/DT=1 PB=0 DR/DT=0 SDEN SCLK SDATA P
CHAPTER 13 13.1 PROGRAMMABLE I/O PINS OVERVIEW Thirty-two pins on the Am186ER and Am188ER microcontrollers are available as userprogrammable I/O signals (PIOs). Each of these pins can be used as a PIO if the normal function of the pin is not needed. If a pin is enabled to function as a PIO signal, the normal function is disabled and does not affect the pin. A PIO signal can be configured to operate as an input or output with or without internal pullup or pulldown resistors, or as an opendrain output.
Table 13-1 PIO Pin Assignments and Register Bits PIO No.
13.2 PIO MODE REGISTERS Table 13-2 shows the possible settings for the PIO Mode and PIO Direction bits. The Am186ER and Am188ER microcontrollers default the 32 PIO pins to either 00b (normal operation) or 01b (PIO input with weak internal pullup or pulldown enabled). Pins that default to active High outputs at reset are pulled down. All other pins are pulled up or are normal operation. See Table 13-2. The column titled Power-On Reset Status in Table 13-1 lists the defaults for the PIOs.
13.3 PIO DIRECTION REGISTERS Each PIO is individually programmed as an input or output by a bit in one of the PIO Direction registers (see Figure 13-4 and Figure 13-5). Table 13-2, “PIO Mode and PIO Direction Settings,” on page 3 shows the values that the PIO mode bits and the PIO direction bits can encode. The column titled Power-On Reset State in Table 13-1 lists the reset default values for the PIOs.
13.4 PIO DATA REGISTERS If a PIO pin is enabled as an output, the value in the corresponding bit in one of the PIO Data registers (see Figure 13-6 and Figure 13-7) is driven on the pin with no inversion (Low=0, High=1). If a PIO pin is enabled as an input, the value on the PIO pin is reflected in the value of the corresponding bit in the PIO Data register, with no inversion. Bits in the PIO Data registers have the same correspondence to pins as bits in the PIO Mode registers and PIO Direction registers.
13-6 Programmable I/O Pins
APPENDIX A REGISTER SUMMARY This appendix summarizes the peripheral control block registers. Table A-1 lists all the registers. Figure A-1 shows the layout of each of the internal registers. The column titled Comment in Table A-1 is used to identify the specific use of interrupt registers when there is a mix of master mode and slave mode usage. The registers that are marked as Slave & master can have different configurations for the different modes.
Table A-1 Internal Register Summary Hex Offset A-2 Mnemonic Register Description FE RELREG Peripheral control block relocation register F6 RESCON Reset configuration register F4 PRL F0 PDCON Power-save control register E4 EDRAM Enable RCU register E2 CDRAM Clock prescaler register E0 MDRAM Memory partition register D8 D1TC D6 D1DSTH DMA 1 destination address high register D4 D1DSTL DMA 1 destination address low register D2 D1SRCH DMA 1 source address high register D0 D1S
Table A-1 Internal Register Summary (continued) Hex Offset Mnemonic Register Description Comment 5C T1CMPB Timer 1 maxcount compare B register 5A T1CMPA Timer 1 maxcount compare A register 58 T1CNT Timer 1 count register 56 T0CON Timer 0 mode/control register 54 T0CMPB Timer 0 maxcount compare B register 52 T0CMPA Timer 0 maxcount compare A register 50 T0CNT 44 SPICON Serial port interrupt control register Master mode 42 WDCON Watchdog timer interrupt control register Master
Figure A-1 Internal Register Summary Offset (Hexadecimal) 15 7 0 R19–R8 FE Res S/M Res M/IO Peripheral Control Block Relocation Register (RELREG) Page 4-4 15 7 0 7 0 RC F6 Reset Configuration Register (RESCON) Page 4-5 15 Reserved PRL F4 Processor Release Level Register (PRL) Page 4-6 15 7 0 F0 0 0 0 0 0 0 0 0 F2–F0 CBF CBD CAF CAD PSEN Power-Save Control Register (PDCON) Page 4-7 7 15 E4 E 0 0 0 0 0 0 0 T8–T0 Enable RCU Register (EDRAM) Page 7-2 7 15 E2 0 0
Figure A-1 Internal Register Summary (continued) 15 7 E0 0 M6–M0 RA19 0 0 0 0 0 0 0 0 0 RA13 Memory Partition Register (MDRAM) Page 7-1 15 7 TC DA DM/IO DDEC DINC SM/IO SDEC INT SYN 0 P Res CHG ST B/W TDRQ SINC DMA 1 Control Register (D1CON) Page 10-3 15 7 D8 0 TC15–TC0 DMA 1 Transfer Count Register (D1TC) Page 10-5 15 7 Reserved D6 0 DDA19–DDA16 DMA 1 Destination Address High Register (D1DSTH) Page 10-6 15 7 0 DDA15–DDA0 D4 DMA 1 Destination Address Low Register
Figure A-1 Internal Register Summary (continued) 15 7 TC CA DM/IO DDEC DINC SM/IO SDEC INT 0 SYN P Res CHG ST B/W TDRQ SINC DMA 0 Control Register (D0CON) Page 10-3 15 7 0 TC15–TC0 C8 DMA 0 Transfer Count Register (D0TC) Page 10-5 15 7 Reserved C6 0 DDA19–DDA16 DMA 0 Destination Address High Register (D0DSTH) Page 10-6 15 7 0 DDA15–DDA0 C4 DMA 0 Destination Address Low Register (D0DSTL) Page 10-7 7 15 DSA19–DSA16 Reserved C2 0 DMA 0 Source Address High Register (D0SRCH
Figure A-1 Internal Register Summary (continued) 15 7 BA19–BA15 AC SR 0 Reserved RE Internal Memory Chip Select Register (IMCS) Page 6-3 15 A8 7 1 M6–M0 EX 0 MS 1 1 1 R2 R1–R0 PCS and MCS Auxiliary Register (MPCS) Page 5-10 15 7 BA19–BA13 A6 1 0 1 1 1 1 1 R2 R1–R0 Midrange Memory Chip Select Register (MMCS) Page 5-8 7 15 BA19–BA11 A4 0 1 1 1 R3 R2 R1–R0 Peripheral Chip Select Register (PACS) Page 5-12 15 A2 0 7 UB2–UB0 1 1 1 1 R7 0 PSE 1 1 1 R2 R1–R0
Figure A-1 Internal Register Summary (continued) 15 7 0 BAUDDIV 88 Serial Port Baud Rate Divisor Register (SPBAUD) Page 11-7 15 7 0 RDATA Reserved 86 Serial Port Receive Data Register (SPRD) Page 11-6 7 15 0 TDATA Reserved 84 Serial Port Transmit Data Register (SPTD) Page 11-5 15 7 0 FER PER OER Reserved 82 Serial Port Status Register (SPSTS) Page 11-4 TEMT THRE RDR BRKI 15 7 Reserved 80 BRK 0 PMODE TXIE RXIE LOOP BRKVAL STP WLGN RSIE TMODE RMODE Serial Port Control Registe
Figure A-1 Internal Register Summary (continued) 15 7 0 PDIR31–PDIR16 78 PIO Direction 1 Register (PDIR1) Page 13-4 15 7 0 PMODE31–PMODE16 76 PIO Mode 1 Register (PIOMODE1) Page 13-3 15 7 0 PDATA15–PDATA0 74 PIO Data 0 Register (PDATA0) Page 13-5 15 7 0 PDIR15–PDIR0 72 PIO Direction 0 Register (PDIR0) Page 13-4 15 7 0 PMODE15–PMODE0 70 PIO Mode 0 Register (PIOMODE0) Page 13-3 7 15 66 EN INH INT 0 0 0 0 0 0 Timer 2 Mode/Control Register (T2CON) Page 9-5 Register Summary
Figure A-1 Internal Register Summary (continued) 7 15 62 0 TC15–TC0 Timer 2 Maxcount Compare A Register (T2CMPA) Page 9-7 7 15 60 0 TC15–TC0 Timer 2 Count Register (T2CNT) Page 9-6 15 5E EN 7 INH INT RIU 0 0 0 0 0 0 0 MC RTG P EXT ALT Timer 1 Mode/Control Register (T1CON) Page 9-3 CONT 15 7 0 TC15–TC0 5C Timer 1 Maxcount Compare B Register (T1CMPB) Page 9-7 7 15 5A 0 TC15–TC0 Timer 1 Maxcount Compare A Register (T1CMPA) Page 9-7 7 15 58 0 TC15–TC0 Timer 1 Count Registe
Figure A-1 Internal Register Summary (continued) 7 15 54 0 TC15–TC0 Timer 0 Maxcount Compare B Register (T0CMPB) Page 9-7 15 7 52 0 TC15–TC0 Timer 0 Maxcount Compare A Register (T0CMPA) Page 9-7 7 15 0 TC15–TC0 50 Timer 0 Count Register (T0CNT) Page 9-6 7 15 (1) Res MSK Reserved 44 0 PR2–PR0 Serial Port Interrupt Control Register (SPICON) Master Mode Page 8-20 7 15 Reserved 42 0 MSK PR2–PR0 Watchdog Timer Interrupt Control Register (WDCON) Master Mode Page 8-19 15 7 Reserved 40
Figure A-1 Internal Register Summary (continued) 7 15 0 LTM Reserved 3E MSK PR2–PR0 INT3 Control Register (I3CON) Master Mode Page 8-16 7 15 0 Reserved 3C LTM MSK PR2–PR0 INT2 Control Register (I2CON) Master Mode Page 8-16 7 15 0 Reserved 3A C PR2–PR0 SFNM INT1 Control Register (I1CON) Master Mode Page 8-14 7 15 0 MSK Reserved 3A LTM MSK PR2–PR0 Timer 2 Interrupt Control Register (T2INTCON) Slave Mode Page 8-30 7 15 Reserved 38 C PR2–PR0 7 15 Reserved Timer 1 Interru
Figure A-1 Internal Register Summary (continued) 7 15 0 Reserved 36 MSK PR2–PR0 DMA 1 Interrupt Control Register (DMA1CON) Master Mode—Page 8-18 Slave Mode—Page 8-30 7 15 34 0 Reserved MSK PR2–PR0 DMA 0 Interrupt Control Register (DMA0CON) Master Mode—Page 8-18 Slave Mode—Page 8-30 7 15 0 Reserved 32 MSK PR2–PR0 Timer Interrupt Control Register (TCUCON) Master Mode—Page 8-18 Timer 0 Interrupt Control Register (T0INTCON) Slave Mode—Page 8-30 7 15 0 TMR2–TMR0 Reserved 30 DHLT Inter
Figure A-1 Internal Register Summary (continued) 7 15 0 Reserved 2E D1 TMR2 D0 Res TMR1 TMR0 Interrupt Request Register (REQST) Slave Mode Page 8-32 7 15 Reserved 2C SPI WD I4 I3 0 I2 I1 I0 D1 D0 Res TMR In-Service Register (INSERV) Master Mode Page 8-23 7 15 0 Reserved 2C D1 TMR2 D0 Res TMR1 TMR0 In-Service Register (INSERV) Slave Mode Page 8-33 7 15 0 Reserved 2A PRM2–PRM0 Priority Mask Register (PRIMSK) Master Mode—Page 8-24 Slave Mode—Page 8-34 7 15 28 Reser
Figure A-1 Internal Register Summary (continued) 7 15 Reserved 28 0 D1 D0 Res TMR2 TMR1 Interrupt Mask Register (IMASK) Slave Mode Page 8-35 TMR0 7 15 Reserved 26 0 S4–S0 IREQ Poll Status Register (POLLST) Master Mode Page 8-26 7 15 Reserved 24 0 S4–S0 IREQ Poll Register (POLL) Master Mode Page 8-27 7 15 Reserved 22 0 S4–S0 NSPEC End-of-Interrupt Register (EOI) Master Mode Page 8-28 7 15 22 Reserved 0 L2–L0 Specific End-of-Interrupt Register (EOI) Slave Mode Page 8-36 Register
Figure A-1 Internal Register Summary (continued) 7 15 Reserved 20 0 T4–T0 0 0 0 Interrupt Vector Register (INTVEC) Slave Mode Page 8-37 7 15 SR Reserved 18 0 Synchronous Serial Receive Register (SSR) Page 12-6 7 15 SD Reserved 16 0 Synchronous Serial Transmit 0 Register (SSD0) Page 12-5 15 7 SD Reserved 14 0 Synchronous Serial Transmit 1 Register (SSD1) Page 12-5 7 15 Reserved 12 0 SCLKDIV Res DE1 DE0 Synchronous Serial Control Register (SSC) Page 12-4 15 10 7 PB Res
INDEX A B A1 signal (Latched Address Bit 1), 3-8 A19-A0 signals (Address Bus), 3-1 A2 signal (Latched Address Bit 2), 3-9 AD15-AD8 signals (Address and Data Bus), 3-2 AD7-AD0 signals (Address and Data Bus), 3-1 Address generation, 2-3 Addressing modes, 2-10 ADEN signal (Address Enable), 3-3, 3-12 AF bit (Auxiliary Carry) Processor Status Flags Register, 2-3 ALE signal (Address Latch Enable), 3-2 ALT bit (Alternate Compare Bit) Timer 0 Mode/Control Register, 9-4 Timer 1 Mode/Control Register, 9-4 Am186ER
DHLT (DMA Halt), 8-21, 8-31 DINC (Destination Increment), 10-3 DM/IO (Destination Address Space Select), 10-3 DR/DT (Data Receive/Transmit Complete), 12-3 DSA15-DSA0 (DMA Source Address Low), 10-9 DSA19-DSA16 (DMA Source Address High), 10-8 E (Enable RCU), 7-2 EN (Enable Bit), 9-3, 9-5 EX (Pin Selector), 5-11 EXT (External Clock Bit), 9-4 FER (Framing Error), 11-4 I4-I0 (Interrupt In-Service), 8-23 I4-I0 (Interrupt Mask), 8-25 I4-I0 (Interrupt Requests), 8-22 IF (Interrupt-Enable Flag), 2-3 INH (Inhibit Bit
ZF (Zero Flag), 2-3 Block diagram, 1-4–1-5 BRK bit (Send Break), 11-2 BRKI bit (Break Interrupt), 11-4 BRKVAL bit (Break Value), 11-2 Bus interface unit, 3-21 nonmultiplexed address, 3-21 operation, 3-18 read and write timing, 3-19–3-20 Byte write enables, 3-21 C C bit (Cascade Mode), 8-14 CAD bit (CLKOUTA Drive Disable) System Configuration Register, 4-7 CAF bit (CLKOUTA Output Frequency) System Configuration Register, 4-7 Carry Flag bit, 2-3 Cascade mode, 8-11 Catalog, xiv CBD bit (CLKOUTB Drive Disable)
DMA 1 Destination Address High Register, 10-6 DMA 1 Destination Address Low Register, 10-7 DMA 1 Interrupt Control Register Master mode, 8-18 Slave mode, 8-30 DMA 1 Source Address High Register, 10-8 DMA 1 Source Address Low Register, 10-9 DMA 1 Transfer Count Register, 10-5 Documentation, iii, xiv Double word data type, 2-8 DR/DT bit (Data Receive/Transmit Complete), 12-3 DRQ1-DRQ0 signals (DMA Requests), 3-4 DSA15-DSA0 field (DMA Source Address Low), 10-9 DSA19-DSA16 field (DMA Source Address High), 10-8
Master mode, 8-16 INT2 signal (Maskable Interrupt Request 2), 3-6 INT3 Control Register Master mode, 8-16 INT3 signal (Maskable Interrupt Request 3), 3-6 INT4 Control Register Master mode, 8-17 INT4 signal (Maskable Interrupt Request 4), 3-6 INTA0 signal (Interrupt Acknowledge 0), 3-6 INTA1 signal (Interrupt Acknowledge 1), 3-6 Integer data type, 2-8 Internal memory debug modes, 6-2 disable, 6-2 external RAM interaction, 6-1 show read enable, 6-2 Interrupt acknowledge, 8-8 Interrupt conditions and sequence,
Midrange Memory Chip Select Register, 5-8 MS bit (Memory/I/O Space Selector), 5-11 MSK bit (Interrupt Mask) description, 8-2 DMA Interrupt Control Registers, 8-18 Timer Interrupt Control Registers, 8-18 MSK bit (Mask) DMA Interrupt Control Registers, 8-30 INT0 Control Register, 8-14 INT1 Control Register, 8-14 INT2 Control Register, 8-16 INT3 Control Register, 8-16 INT4 Control Register, 8-17 Serial Port Interrupt Control Register, 8-20 Timer Interrupt Control Registers, 8-30 Watchdog Timer Interrupt Contro
Processor Status Flags Register (FLAGS), 2-2 Product support bulletin board service, iii documentation and literature, iii technical support hotline, iii PSE bit (PSRAM Mode Enable), 5-7 Pseudo Static RAM (PSRAM) support, 3-21 Pullup/pulldown resistor, 13-3 Q Quad word data type, 2-8 R R19-R8 field (Relocation Address Bits), 4-4 R1-R0 field (Wait State Value) Low Memory Chip Select Register, 5-7 Midrange Memory Chip Select Register, 5-9 PCS and MCS Auxiliary Register, 5-11 Peripheral Chip Select Register,
Power-Save Control (PDCON, Offset F0h), 4-7 Priority Mask (PRIMSK, Offset 2Ah), 8-24, 8-34 Processor Release Level (PRL, Offset F4), 4-6 Reset Configuration (RESCON, Offset F6h), 4-5 Serial Port Baud Rate Divisor (SPBAUD, Offset 88h), 11-7 Serial Port Control (SPCT, Offset 80h), 11-2 Serial Port Interrupt Control (SPICON, Offset 44h) Master mode, 8-20 Serial Port Receive Data (SPRD, Offset 86h), 11-6 Serial Port Status (SPSTS, Offset 82h), 11-4 Serial Port Transmit (SPTD, Offset 84h), 11-5 Specific End-of-I
DEN (Data Enable), 3-4 DRQ1-DRQ0 (DMA Requests), 3-4 DT/R (Data Transmit or Receive), 3-4 HLDA (Bus Hold Acknowledge), 3-4 HOLD (Bus Hold Request), 3-5 IMDIS (Internal Memory Disable), 3-13 INT0 (Maskable Interrupt Request 0), 3-5 INT1 (Maskable Interrupt Request 1), 3-5 INT2 (Maskable Interrupt Request 2), 3-6 INT3 (Maskable Interrupt Request 3), 3-6 INT4 (Maskable Interrupt Request 4), 3-6 INTA0 (Interrupt Acknowledge 0), 3-6 INTA1 (Interrupt Acknowledge 1), 3-6 IRQ (Slave Interrupt Request), 3-6 LCS (Low
Timer 1 Count Register, 9-6 Timer 1 Interrupt Control Register Slave mode, 8-30 Timer 1 Maxcount Compare A Register, 9-7 Timer 1 Maxcount Compare B Register, 9-7 Timer 1 Mode and Control Register, 9-3 Timer 2 Count Register, 9-6 Timer 2 Interrupt Control Register Slave mode, 8-30 Timer 2 Maxcount Compare B Register, 9-7 Timer 2 Mode and Control Register, 9-5 TImer Interrupt Control Register Master mode, 8-18 Times Four mode, 3-23 Times One mode, 3-23 Timing characteristics, xiv TMODE bit (Transmit Mode), 11
