AMD SB600 BIOS Developer’s Guide (Public Version) Technical Reference Manual Rev. 3.00 P/N: 46157_sb600_bdg_pub_3.00 ©2008 Advanced Micro Devices, Inc.
Trademarks AMD, the AMD Arrow, ATI, the ATI logo, Radeon, Mobility Radeon, AMD Athlon, Sempron, Turion and combinations thereof are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Microsoft and Windows are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Table of Contents 1 Introduction ................................................................................................................. 7 1.1 About This Manual........................................................................................................................ 7 1.2 Overview ....................................................................................................................................... 7 1.3 PCI Internal Devices ..........................................
6.1 IDE Channel Enable/Disable....................................................................................................... 27 6.1.1 IDE Channel Enable ............................................................................................................................27 6.1.2 IDE Channel Disable ...........................................................................................................................27 6.2 PIO Modes.........................................................
12 High Precision Event Timer (HPET) ...................................................................... 44 12.1 Initialization ................................................................................................................................ 44 12.1.1 Sample Initialization Code...................................................................................................................44 12.2 ACPI HPET Description Table ................................................................
14.6.4 ACPI Programming .............................................................................................................................72 14.7 SATA Hot Plug Sample Program ............................................................................................... 74 14.8 Temperature Limit Shutdown through SMI# .............................................................................. 80 14.8.1 Setting Up ITE 8712 Super I/O Registers ....................................................
1 Introduction 1.1 About This Manual This manual provides guidelines for BIOS developers working with the AMD SB600. It describes the BIOS and software modifications required to fully support the device. Note: To help the reader to readily identify changes/updates in this document, changes/updates over the previous revision are highlighted in red. Refer to Appendix: Revision History at the end of this document for a detailed revision history. 1.
Supports LPC DMA 6/8 channel support on audio codec Supports type F DMA Multiple functions for audio and modem Codec operations LPC host bus controller Bus master logic Supports LPC based super I/O and flash devices Supports up to 3 codecs simultaneously Supports SPDIF output Supports two master/DMA devices Separate bus from the HD audio Supports TPM version 1.1/1.
Power Management ACPI specification 2.
1.3 PCI Internal Devices This section contains two block diagrams for the SB600. Figure 1 shows the SB600 internal PCI devices with their assigned bus, device, and function numbers. Figure 2 shows the SB600 internal PCI devices and the major function blocks.
ALINK-EXPRESS II AB 4 PORTS B-LINK A-LINK PORT 1 PORT 0 AC97 Audio SATA Controller AC97 AC97 Modem B-LINK 10 PORTS HD Audio USB:OHCI USB:EHCI Debug port ALINK 1 CHANNEL IDE LPC bus SMBUS /ACPI LPC PCI Bridge SPI bus 6 PCI SLOTS ROM X1/X2 BUS Controler XBUS SERIRQ# RTC SIRQ APIC PIC PICD[0] RTC_IRQ#, PIDE_INTRQ, SIDE_INTRQ, USB_IRQ#, AC97INTAB, AC97INTBB GPIO BM 8250 TIMER SPEAKER INTERRUPT controller ACPI / HW Monitor SMI INTR IGNNE#, FERRB#, INT# F:A SMBUS GEVENT[7:0],S
2 SB600 Programming Architecture 2.
2.2 I/O Map The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but can be disabled in some cases. Variable ranges are configurable. 2.2.1 Fixed I/O Address Ranges 2.2.1.1 Fixed I/O Address Ranges – SB600 Proprietary Ports I/O Address C00h-C01h C14h C50h-C51h C52h C6Fh CD0h-CD1h CD4h-CD5h CD6h-CD7h 2.2.
* Note: • • • • The SMI CMD Block must be defined on the 16-bit boundary, i.e., the least significant nibble of the address must be zero (for example, B0h, C0h etc.) The SMI CMD Block consists of two ports – the SMI Command Port at base address, and the SMI Status Port at base address+1. The writes to SMI Status Port will not generate an SMI. The writes to the SMI Command Port will generate an SMI.
3 SB600 Early-POST Initialization The system BIOS needs to configure the SB600 at the very beginning of POST. Some of the settings will change depending on the OEM design, or on the newer revision chipset. 3.1 512K/1M ROM Enable With the SB600 design, there can be two possible ROM sources: PCI ROM and LPC ROM. Two pin straps (UseLpcRom, FWHDisable) decide where the ROM is (see the SB600 databook). Upon system power on, the SB600 enables 256K ROM by default.
Register 50h, 54h, 58h, 5ch of Device 14h, Function 3 Field Name Base Address Bits 31:11 Length 10:2 Read Protect 1 Write Protect 0 Description ROM Base address. The most significant 21 bits of the base address are defined in this field. Bits 10:0 of the base address are assumed to be zero. Base address, therefore, is aligned at a 2K boundary. These 9 bits (0-511) define the length from 1K to 512K in increments of 1K. When set, the memory range defined by this register is read protected.
3.2 Real Time Clock (RTC) 3.2.1 RTC Access The internal RTC is divided into two sections: the clock and alarm function (registers 0 to 0Dh), and CMOS memory (registers 0Eh to FFh). The clock and alarm functions must be accessed through I/O ports 70h/71h. The CMOS memory (registers 0Eh to FFh) should be accessed through I/O ports 72h/73h. 3.2.1.1 Special Locked Area in CMOS Some CMOS memory locations may be disabled for read/write.
3.3 BIOS RAM The SB600 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h. 3.4 Serial IRQ The SB600 supports serial IRQ, which allows one single signal to report multiple interrupt requests. The SB600 supports a message for 21 serial interrupts, which include 15 IRQs, SMI#, IOCHK#, and 4 PCI interrupts. SMBus PCI Reg69h is used for setting serial IRQ.
3.5 SubSystemID and SubSystem Vendor ID SubSytem ID and SubSystem Vendor ID can be programmed in various functions of SB600 register 2Ch. These registers are write-once registers. For example, to program a SubSystem vendor ID of 1002h and SubSystem ID of 4341h in AC97 device 14h, function 5, use the following assembly language sample code: mov eax,8000A52Ch mov dx,0CF8h out dx,eax mov dx,0CFCh mov eax,43411002h out dx,eax 3.
3.7 System Restart after Power Fail The way the system restarts following the power-fail/ power-restore cycle depends both on the PMIO register 74h [bits 1:0], and the hardware jumper on the SB600 pin ACPWR_Strap. PMIO Register 74h bits[1:0] 00b 01b 10b 11b Description The system restart will depend on the ACPWR_Strap pin pull up/down state. Pin = 0 : The system will restart without pressing the power button Pin = 1 : The system will remain off until the power button in pressed.
4 PCI IRQ Routing 4.1 PCI IRQ Routing Registers The SB600 uses one pair of I/O ports to do the PCI IRQ routing. The ports are at C00h/C01h. Address C00h Register Name PCI_Intr_Index C01h PCI_Intr_Data Description PCI IRQ Routing Index 0 – INTA# 1 – INTB# 2 – INTC# 3 – INTD# 4 – SCI 5 – SMBus interrupt 9 – INTE# 0Ah – INTF# 0Bh – INTG# 0Ch – INTH# 0 ~ 15 : IRQ0 to IRQ15 IRQ0, 2, 8, 13 are reserved 4.
4.3 Integrated PCI Devices IRQ Routing In the SB600, the AC’97 and USB need PCI IRQ. Internally, they are routed to different PCI INT#s.
4.4 PCI IRQ Routing for APIC Mode PCI IRQ INTA# INTB# INTC# INTD# INTE# INTF# INTG# INTH# APIC Assignment 16 17 18 19 20 21 22 23 © 2008 Advanced Micro Devices Inc.
5 SMBus Programming The SB600 SMBus (System Management Bus) complies with SMBus Specification Version 2.0. 5.1 SMBus I/O Base Address The BIOS needs to set a valid SMBus I/O base address before enabling the SMBus Controller. There are two places at which the BIOS is able to set the SMBus I/O base addresses: one is at PCI Reg10h, another is at PCI Reg90h, and both are on the SMBus Controller (Bus 0, Device 14h, Function 0).
The power-up default value in register 0Eh is A0h, therefore the default frequency is (66MHz)/(160 * 4), or approximately 103 KHz. The minimum SMBus frequency can be set with the value FFh in the register at index 0Eh, which yields: (66MHz)/(255*4) = 64.7 KHz. 5.3 SMBus Host Controller Programming Step Descriptions Register in SMBus I/O Space Reg00h[Bit0] 1 Wait until SMBus is idle. 2 3 4 7 Clear SMBus status. Set SMBus command.
© 2008 Advanced Micro Devices Inc.
6 IDE Controller The SB600 IDE controller supports Ultra ATA 33/66/100/133 modes. The IDE controller can be configured into either the compatible mode or the native mode. Under the compatible mode, the IDE controller will use the legacy resources. The SB600 allows programming of the IDE timing and mode for each drive independently on each channel. 6.1 IDE Channel Enable/Disable Register on IDE Controller Reg09h Reg48h Reg48h Bit 1 0 8 Description Primary IDE channel programmable logic enable.
6.2 PIO Modes The SB600 supports IDE PIO mode 0, 1, 2, 3, and 4. For PIO mode selection, the BIOS needs to program not only the PIO mode register, but also the PIO timing register. 6.2.1 PIO Mode The BIOS can simply give the PIO mode number through Reg4Ah on the IDE controller. 6.2.2 PIO Timing Two parameters determine the PIO bus-cycle timing: the command width and the recovery width.
6.3.2 Ultra-DMA Mode The SB600 IDE controller supports UDMA mode 0, 1, 2, 3, 4, 5, and 6. It only takes two simple steps to program the SB600 IDE controller into the UDMA mode: 1. Set the mode number in UDMA mode register (Reg56h). 2. Enable the UDMA mode through the UDMA control register (Reg54h). The UDMA buscycle timing is fixed after the UDMA mode is selected. UDMA Mode 0 1 2 3 4 5 6 Bus-Cycle Timing (ns) 120 90 60 45 30 20 15 © 2008 Advanced Micro Devices Inc.
7 Serial ATA (SATA) The SB600 has two SATA devices. For ASIC revision A21, they are at Bus 0, Device 12h, Function 0 and Bus 0, Device 11h, Function 0. For revisions A11 and A12, they are at Bus 0, Device 13h, Function 3 and Function 4. The SATA devices are enabled/disabled through a register at ADh in the SMBus controller (Device 14h, function 0).
8 Power Management On the SB600, PM registers can be accessed through I/O ports CD6h/CD7h. Before initiating any power management functions in the SB600, the BIOS needs to set the I/O base addresses for the ACPI I/O register, the SMI Command Port, etc.
I/O Name Description Configure Register Enable Status PIO4 Programmable I/O Range 4 PM IO RegA0 & RegA1h PM IO Reg A8h[Bit0] PM IO RegA9h[Bit0] PIO5 Programmable I/O Range 5 PM IO RegA2 & RegA3h PM IO Reg A8h[Bit1] PM IO RegA9h[Bit1] PIO6 Programmable I/O Range 6 PM IO RegA4 & RegA5h PM IO Reg A8h[Bit2] PM IO RegA9h[Bit2] PIO7 Programmable I/O Range 7 PM IO RegA6 & RegA7h PM IO Reg A8h[Bit3] PM IO RegA9h[Bit3] Note: PM IO Reg04h[Bit7] is the overall control bit for enabling all the PIOs.
PM IO register 53h bit [3] = 0 SMI# enabled (default) PM IO register 53h bit [3] = 1 SMI# disabled (all events disabled) SMI Source Software SMI (obsolete way) Software SMI Description Set SmiReq (PM IO Reg00h[Bit4]) to generate SMI. Any writing to SMI Command port. PM Timer 1 Timeout on PM Timer 1. Activity on PM IO register 08h, 09h, 0Ah will retrigger timer PM Timer 2 Timeout on PM Timer 2. (See section 9.3.2) IRQ[15:8] IRQ[15:8] activity.
8.4.1 Power Button Power button is always a wake-up event and can be programmed as an SCI wake-up event. The power button status register is AcpiPmEvtBlk, bit[8]. The BIOS must make sure this bit is cleared prior to the entry into any C or S states. In addition, when the power button is pressed for 4 seconds, the SB600 will shut down the entire system (by going to S5). No programming is required for this function. 8.5 C-State Break Events 8.5.
• PCI registers not on the SB600 • Super I/O and other I/O registers. The BIOS typically sets aside an area in the memory to save the registers prior to the S3 state. The Southbridge registers may be saved in any order as long as those registers are visible to the BIOS. Some of the registers, such as SubSystem ID and SubSystem Vendor ID, may be saved, but written only once as dword. They are handled separately during restore. 8.7 Wake on Events TBD 8.
System BIOS has to follow the sequence below: 1. 2. 3. 4. 5. Disable Sleep SMI Control register (SLP_SMI_EN). Software workaround or system BIOS debugging routing implementation. Write SLP_SMI_Status 1 to clear this event. Rewrite sleep command to ACPI register (ACPI PM1_CNT). RSM if necessary. © 2008 Advanced Micro Devices Inc.
9 APIC Programming With the AMD integrated chipset solution, the BIOS needs to program both the Northbridge and the Southbridge in order to support APIC. 9.1 Northbridge APIC Enable There are three bits in the Northbridge that the BIOS should set before enabling APIC support. • • • Enable Local APIC in AMD Athlon processors. (Set bit11 in APIC_BASE MSR(001B) register.) Reg4C[bit1] - This bit should be set to enable. It forces the CPU request with address 0xFECx_xxxx to the Southbridge.
9.5 APIC IRQ Routing During the BIOS POST, the BIOS will do normal PCI IRQ routing through port C00h/C01h. Once APIC is fully enabled by the OS, the routing in C00h/C01 must be all cleared to zero. The following is a sample ASL code that may be incorporated into the BIOS: Name(PICF,0x00) Method(_PIC, 0x01, NotSerialized) { Store (Arg0, PICF) If(Arg0) { \_SB.PCI0.LPC0.
10 Watchdog Timer To enable the watchdog timer in the SB600, the following registers must be initialized: • • • Enable the watchdog timer by resetting bit 0 in PMIO register 069h. Set bit 3 in SMBus PCI Config (Bus 0 Device 20 Function 0) Reg 41h to enable the watchdog decode. Ensure that the watchdog timer base address is set to a non zero value, typically 0FEC000F0h. The watchdog base address is set at PMIO address 6Ch-6Fh as shown in the sample program below.
mov dx,0CD6h ; PMIO index register mov al,6Ch ; Least significant base address location out dx,al ; Set the index to 6Ch mov dx,0CD7h ; PMIO data register mov al,0F0h out dx,al ; Least significant base address To verify that the watchdog timer works correctly, perform the following steps: • • • Write 100 (count) to the watchdog count register at address 0FEC000F4h. Enable and start the watchdog timer by writing 00000081h to the watchdog control register at 0FEC000F0h.
11 A-Link Bridge 11.1 A-Link Registers The registers are accessed using an address-register/data-register mechanism. The address register is AB_INDX[31:0], and the data register is AB_DATA[31:0]. 31:30 RegSpace[1:0] 29:17 Reserved 16:2 Register address[16:2] 1:0 Reserved AB_INDX [31:0] 31:0 Data[31:0] AB_DATA[31:0] RegSpace[1:0] 00b 01b 10b 11b AXINDC Index/Data Registers.
Register Indirect Address AX_INDXC 30h AX_DATAC 34h AX_INDXP 38h AX_DATAP 3Ch Example: To write to register 21h in the INDXC space with a data of 00, the following steps are required: 1. Out 30h to AB_INDX. This will prepare to write register from INDXC 2. Out 21h to AB_DATA. This will set register 21h of INDXC 3. Out 34h to AB_INDX. This will prepare to write data to register defined in steps 1 and 2 above 4. Out 00 to AB_DATA.
mov eax, 0C0000090h ; Bits[31:30] = 11 for A-Link Bridge register ; space out dx,eax ; Register index is set mov dx,0c84h ; I/O address for data mov eax,00000001h ; Power down 2 lanes to save power out dx,eax Read: Use a similar indirect procedure to read out the register value inside AB and BIF. © 2008 Advanced Micro Devices Inc.
12 High Precision Event Timer (HPET) The SB600 includes an industry standard High Precision Event Timers (HPET). The details and the operation of the timer are described in the IA-PC HPET specification. This section describes the timer initialization in the SB600 chipset. 12.1 Initialization For SB600 is HPET usage is required, then during the early POST, the timer base address must be programmed in Device 14h, Function 0, register 14h.
12.2 ACPI HPET Description Table As described in the specification, an ACPI HPET table is required to report the base address to the operating system. The table includes a ACPI table header, and HPET table-specific fields.
13 Common Interface Module – CIM-SB600 13.1 CIM-SB600 Architecture CIM-SB600 employs a modular component design with an open interface definition such that the amount of functional components included, the sequence these components are called, and the way these components are called could all be different, depend on different requirements of different OEM projects/platforms. CIM-SB600 requires bios code base provides addresses (for ex. SMBUS Base Address).
System PowerOn SBCIM - SBPOR Initialization Module CPU Initialization, NorthBridge Initialization Restore memory controller configuration etc Is S3 resume? Memory detection. System BIOS shadowing NO Yes SBCIM Post Initialization submodule – AtiSbBeforePciInit 1. Reads the PCIE base address from SBCIM Runtime submodule AtiSbBfPciRestore NorthBridge and saves it for further use to do PCI config using MMIO access. 2. Enable or Disable South Bridge devices depending on input data structure values. 3.
13.2 CIM-SB600 Build Configuration SBCIM module provides the BIOS developer the flexibility to assign their own values (for programmable options such as SMBUS port address). SB module configuration requirement from BIOS code base: Override Symbol ATI_BIOS_SIZE ATI_SMBUS_BASE_ADDRESS ATI_SIO_PME_BASE_ADDRESS sb_acpi_base_tbl: acpi_base STRUC pm1evt dw ? pm1ctr dw ? pmtmr dw ? cpuctr dw ? gpe0 dw ? smicmd dw ? pmactl dw ? ssctl dw ? acpi_base ends ATI_ACPI_WDRT_BASE Description BIOS FlashROM size.
ATI_SB_CFG_STRUCT ACAF DD STRUC 0 ; ATI CFG ASL Flags ; BIT0:TPMF ; BIT1:STHP: SATA HOT Plug ; BIT2:SHPG: Second IDE Hot Plug ; BITx:xxxx DB 1 ; 0:None 1:SATA 1 ; 0:IDE 1:RAID 2:AHCI 3 ; 0:disable 1:enable 1 ; 0:disable 1:enable 0 ; 0:AUTO 1:disable 2:enable 0 ; 0:AUTO 1:disable 2:enable DB 0 ; 0:AUTO 1:disable 2:enable 1 ; 0:disable 1:enable 0 ; 0:AUTO 1:disable 2:enable 0 ; 0:Not Detected 1:Detected 0 ; 0:disable 1:enable 0 ; 0:disable 1:enable DB 4 ; 1 byte 0 ; 0:disable 1:enable DB 4 ; 1 byte 0 ; 0:dis
Description of Data Structure Option SATA_CHANNEL Description Enable/Disable SATA controllers SATA_CLASS SATA controller operating mode SATA_SMBUS Enable/Disable SATA SMBUS. There is only one SATA SMBUS (I2C) interface for the two SATA controllers Enable/Disable USB1.1 OHCI controllers. USB11 USB20 Enable/Disable USB2.0 EHCI controller AC97_AUDIO Enable/Disable AC97 controller. MC97_MODEM Enable/Disable MC97 controller. AZALIA Enable/Disable Azalia High Definition (HD) audio controller.
13.4 CIM-SB600 SBPOR Sub-Module Southbridge Power-On Reset initialization (SBPOR) is designed to support initialization of Southbridge registers common across all platforms. Design take in to consideration that code will be executed in stackless environment. There is no inputs requirement for this module except that the return address should be setup in SP. Module files: SB_POR.INC Support files: SB_CMN.INC, ATISBCFG.INC 13.4.
13.5.2 SB POST Interface AtiSbBeforePciInit – This interface should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. The segment where the SBCIM Runtime sub module is included should be made writable before calling this routine, since this interfaces updates some of the variables which are present in the SBCIM runtime module. This routine: 1. 2. 3. 4. 5. 6. 7.
13.6 CIM-SB600 SB Runtime Interface Sub-Module SB Runtime Initialization module is consistent of two parts. 1) Normal boot. 2) S3 resume All the PCI configuration accesses are done using the memory mapped PCI configuration space. Module files: ATISBRT.INC, AM97RT.INC, AZALIAR.INC, SATART.INC, USBRT.INC Support files: ATISBCFG.INC, SB_CMN.INC, SB_CMNPT.INC The entire runtime initialization module is needed during POST and S3 resume and so it should not be discarded at end of BIOS POST.
2. 3. Enables Keyboard reset SMI for P4 platforms. Enables IDE dynamic power savings. 13.7 CIM-SB600 SB SMI Interface Sub-Module SBCIM SMI interface implements workarounds for some of the known hardware issues Module files: SBSMI.INC, KBRST_WA.INC, RTC_WA.INC, SATATRAP.INC, Support files: ATISBCFG.INC, SB_CMN.INC, SB_CMNPT.INC 13.7.1 Requirements The following requirements should be met before calling any interface in the SB SMI module: Stack should be present.
14 Sample Programs 14.1 SB600 Register Initialization on Power-Up 14.1.1 Initialization of PCI IRQ Routing Before Resource Allocation The PCI IRQs are programmed using index/data format through registers C00h/C01h. Index 0 through 3, and 9 through 0Ch, are for PCI IRQ lines. Index 4 is for SCI interrupt generated for ACPI, and Index 5 is for SMBus interrupt. Sample Program The following routine initializes all PCI interrupts to zeroes.
cmp al, 0Ch jbe ClearPciIrq9ToC pop dx pop ax ; Max index in 9 to 0Ch series ; Restore the registers ret PciIrqInit endp 14.2 Setup Options 14.2.1 64 Bytes DMA If 64 bytes DMA is selected for P2P bridge, set PCI to PCI bridge device 14h, function 4, register 4Bh, bit 4 to 1. 14.2.
14.2.3 C3 Support The C3 support depends on the processor PBE support and HyperThreading. The ACPI FACP table also needs to be modified for C3 support. The description below applies only to the SB600 registers affected by C3 support.
pop dx pop eax ; Restore registers ret EnableSubtractiveDecoding endp 14.2.5 Enable/Disable On-Chip SATA SATA may be disabled/enabled by Miscellaneous SATA register located at bus 0, device 14h, function 0, register ADh. Bit 0 of this register, when set to 1, enables SATA.
2. Write to the same SATA device registers (9h, 0Ah, 0Bh) with the class ID. 3. Disable header write: Clear the SATA device register 40h, bit 0 to 0. Sample Program: This sample program will set SATA-1, Bus 0, Device 12h, Function 0 to class code for IDE class 01018Fh. SataClassIdSampleProgram push eax push dx proc near ; Save registers used by this routine ; Enable header write.
pop eax ret SataClassIdSampleProgram endp Note: For SB600 revision A11 and revision A12, the SATA controller was at Bus 0, Device 13h, function 3 and 4. 14.2.7 Disable AC97 Audio or MC97 Modem For, the AC97 PCI device 14h, functions 5 or 6 may be disabled by setting bits in PM I/O register 59h. The setting of bit 0 will mask out AC97 device 14h, function 5. the setting of bit 1 will mask out MC97 device 14h, function 6.
mov dx,0CD6h ; PM I/O index register mov al, 59h ; AC97 Mask register out dx,al mov dx,0CD7h ; PM I/O data register in al,dx ; Read current value or al,01h ; Set AC97 audio to disable out dx,al DisableDone: pop dx pop eax ret DisableAc97Sample endp 14.2.8 Enable EHCI Controller The memory must be in big real mode to access the USB operational registers through the 32-bit base address register.
mov dx,0CFCh mov al, 07h out dx,al ; Issue host controller reset through operational register 0 xor ax,ax mov es,ax mov eax, es:[ebp] or eax,02h mov es:[ebp],eax ; To access operational registers through BAR ; Enables the USB PHY auto calibration resistor mov eax, 00020000h mov es[ebp+0C0h], eax ; Program EHCI FIFO threshold.
14.2.9 Enable OHCI Controller OHCI Device 13h, function 1 and 5, may be enabled/disabled by bits 1 and 5 in SMBus device 14h, function 0, register 068h. If disable is done after BAR resources are allocated, set BAR to zero. USB SMI enabled, when appropriate, at SMBus device 14h, function 0, register 65h, bit 7. Sample Program: Enable 5 OHCIs .
Reg 43h Secondary master timing Reg 4Ah, bits[2:0] Primary master mode number Reg 4Ah bits[6:4] Primary slave mode number Reg 4Bh bits[2:0] Secondary master mode number Reg 4Bh bits[6:4] Secondary slave mode number PIO timing has two components – the command width, and the recovery width.
14.3.2 Multiword DMA Settings IDE multiword DMA setting is done through registers 44h to 47h. The timing for the multiword DMA modes has two components – the command width, and the recovery width.
Sample Program The sample program below sets the primary slave to UDMA mode 5: push eax push dx ; For primary slave, set register 56h, bits [6:4] to 5 for UDMA mode 5 mov dx,0CF8h ; To access PCI configuration space of IDE controller mov eax,8000A154h ; Device 14h, function 1, register space 54h – 57h out dx,eax ; mov dx,0CFEh ; To access register 56h in al,dx ; Current value of register 56h and al,8Fh ; Clear bits 6:4. or al,50h ; Set UDMA 5 mode for primary slave.
push dx mov mov out mov in mov eax,8000A148h dx,0CF8h dx,eax dx,0CFCh ax,dx bx,ax ; To modify register 48h on the IDE controller ; PCI index register ; Set index for register 48h-4Bh ; Set PCI data register for 48h ; Read register 49h ; Save current 48h-49h registers ; Unlock the IDE controller to be enabled/disabled bit mov mov out mov in or out eax,8000A108h dx,0CF8h dx,eax dx,0CFDh al,dx al,08h dx,al ; To write to PCI register 08h on IDE controller ; PCI index register ; Set index for registers 08
14.3.5 IDE Channel Enable The primary IDE channel is enabled as power-on default. To enable an IDE channel after they have been disabled, the BIOS must: 1. Set the IDE channel programmable logic enable bit in Reg09h. 2. Clear the IDE channel disable bit in Reg48h to enable the IDE channel. Note: No IDE I/O port access is allowed between step (1) and step (2). It is recommended that the BIOS execute step (2) immediately after step (1).
mov mov out mov in and out eax,8000A108h dx,0CF8h dx,eax dx,0CFDh al,dx al,0FBh dx,al pop pop pop dx bx eax ; To write to PCI register 08h on IDE controller ; PCI index register ; Set index for registers 08h – 0Bh ; To read register 09h ; Read register 09h ; Clear bit 1 to enable primary channel program ; Write back to register ; End of primary channel enable 14.4 USB Controller Reset at Hard Reset This USB controller reset sequence is not required for SB600 14.
; Get ACPI CLKVALUE register address from PM IO index 26h and 27h mov dx,0CD6h ; Set the PM IO register index mov al, 27h ; Index = High byte, ACPI clock address out dx,al mov dx,0CD7h ; Get PM IO register data in al,dx ; High byte of ACPI clock address mov ah,al ; Save High byte of address mov dx,0CD6h ; Set the PM IO register index mov al, 26h ; Index = Low byte, ACPI clock address out dx,al mov dx,0CD7h ; Get PM IO register data in al,dx ; Low byte of ACPI clock address mov
14.6 Lid Switch The Lid Switch programming is implementation specific. In a typical implementation the output of the debounced lid switch is connected to one of the Gevent or GPM pins. The Gevent and GPM pins can trigger the ACPI event, and the trigger polarity is programmable through the Southbridge register. The Gevent and GPM pins are in S5 plane and hence can trigger the event in S5 state. 14.6.
mov dx,0CD6h ; PMIO index mov al,37h ; out dx,al ; Set PMIO index mov dx,0CD7h ; PMIO data in al,dx ; Read current value and al,0Feh ; Falling edge trigger (on closing the lid) out dx,al ; Enable ExtEvent bit in ACPI GPE0 enable block. mov dx,824h ; GPE0 enable is offset 4 of GPE0 block in eax,dx ; Read GPE0 block or eax,0100h ; Set bit 16, ExeEvent0 enable out dx,eax ; Enable ExtEvent0 to S5 plane. This step is optional as the bit is set by default.
/////////////////////////////////////////////////////////////////////////////////////////////////////////// //Code for Lid Switch control. // // This code is based on Lid switch connected to ExtEvent0.
if(LPOL){Return(0x00)} // Lid is closed else {Return(0x1)} // Lid is open } Name(_PRW, Package(2) { 0x10, 0x03} // ACPI event 0x10 can wake-up from S3 ) } //ACPI event Scope(\_GPE) { Method(_L10) { Not(LPOL, LPOL) // Reverse the polarity from sleep to Notify(\_SB.LID, 0x80) // Notify the OS that status has changed. wake and vice versa } } 14.
// For SATA at Bus 0, Device 12h, Function 0, channel 1 device // Check if change in the status of the Serial ATA PHY if(\_SB_.PCI0.SATA.STA1) { // BAR5, offset 18Ah, bit 0 Notify(\_SB.PCI0.SATA.SECD.S_D0, 0x00) sleep(2000) Notify(\_SB.PCI0.SATA.SECD, 0x01) sleep(2000) store(\_SB_.PCI0.SATA.STA1,\_SB_.PCI0.SATA.STA1) // of slave SAT //clear Status } // For SATA at Bus 0, Device 11h, Function 0 , channel 0 device // Check if change in the status of the Serial ATA PHY if(\_SB_.PCI0.SAT2.
Scope(\_SB_.PCI0.SATA) // Bus 0, Device 12h, Function 0 { OperationRegion(BAR5, SystemMemory, 0xFFF80000, 0x1000) // address should be replaced by the BIOS // The Field(BAR5, AnyAcc, NoLock, Preserve) { Offset(0x104), // Channel 0 CSTX, 1, // Device detected but no communication with Phy CST0, 1, // Communication with Phy established.
Device(P_D0) { Name(_ADR, 0) // Drive 0 - Master Method(_STA,0){ if (\_SB_.PCI0.SATA.CST0) { //If SATA detected return(0x0f) } else { return (0x00) } } End of Method (_STA ) } // End of P_D0 } // End of PRID Device(SECD) { Name(_ADR, 1) // IDE Secondary Channel Device(S_D0) { Name(_ADR, 0) // Drive 0 - Master Method(_STA,0){ if (\_SB_.PCI0.SATA.CST1) { // If SATA detected return(0x0f) } else { return (0x00) } } / // End of Method (_STA) } // End of S_D0 } // End of SECD } // End of Scope(_SB.
// Bus 0, Device 11h, Function 0 Scope(\_SB_.PCI0.
Name(_ADR, 0) // IDE Primary Channel Device(P_D0) { Name(_ADR, 0) // Drive 0 - Master Method(_STA,0){ if (\_SB_.PCI0.SAT2.CST0) { // If SATA detected return(0x0f) } else { return (0x00) } } // End of Method(_STA) } // End of P_D0 } // End of PRID Device(SECD) { Name(_ADR, 1) // IDE Secondary Channel Device(S_D0) { Name(_ADR, 0) // Drive 0 - Master Method(_STA,0){ if (\_SB_.PCI0.SAT2.
14.8 Temperature Limit Shutdown through SMI# The program to shut down the system when the temperature exceeds a pre-set limit requires the following: 1. A temperature sensing diode or thermistor positioned under the CPU socket. 2. A Super I/O device capable of monitoring the temperature and toggle an SMI# line when the temperature exceeds the pre-set limit. 3. SMI programming in the SB600 to shut down the system.
; Logical Device Number (LDN) is now set to 04. ; Set Base address to 0228h in registers 60h and 61h of this LDN = 04 ; Set MS byte of base address to 02h mov mov out dx,2Eh dx,60h dx,al mov mov out dx,2Fh al,02h dx,al ; Super I/O index ; MS byte of 0228h ; Set LS byte of the base address to 28h mov mov out dx,2Eh dx,61h dx,al mov mov out dx,2Fh al,28h dx,al ; Super I/O index ; MS byte of 0228h ; The environment (temperature, voltage etc.
; Register 42h is for upper limit, register 43h is for lower limit ; If lower limit is 7Fh then it is comparator mode mov dx,Sensor_Port mov al,42h out dx,al ; The register is written through index at 22Dh ; To set the upper limit mov dx,Sensor_Port+1 mov al,ah out dx,al ; The temperature value is written through 22Eh ; Get the Temperature upper limit mov dx,Sensor_Port mov al,43h out dx,al ; The register is written through index at 22Dh ; To set the lower limit mov dx,Sensor_Port+1 mov al,7fh out dx,
out dx,al mov dx,Sensor_Port+1 mov al,ah out dx,al mov dx,Sensor_Port mov al,54h out dx,al ; The temperature value is written through 22Eh ; Get temperature upper limit ; The register is written through index at 22Dh ; Thermal limit for thermistor 3 mov dx,Sensor_Port+1 mov al,ah out dx,al ; The temperature value is written through 22Eh ; Get temperature upper limit ; Read status from register 03 to clear the status mov dx,Sensor_Port mov al,03h out dx,al ; The register is read through index at 22Dh
; Register F4 is SMI mapping register mov al,0f4h mov dx,SuperIo_Config_Port out dx,al inc dx mov al,27h out dx,al ; 3.
14.8.2 Initialize Southbridge Registers for SMI# ; Enable the base address range (228h-22Fh) in the LPC register. ; Address range 228h-22Fh is enabled in LPC Device 14h, function 3, Register 45h, bit 1 mov mov out mov in or out dx,0CF8h eax,8000A344h dx,eax dx,0CFDh al,dx al,02h dx,al ; PCI device access index register ; Device 14h, function 3, registers 44h-47h ; To access register 45h ; Read register 45h ; Set bit 1 ; Configure ExtEvent1 for SMI#.
14.8.3 SMI Programming to Shut Down the System The SMI programming should shut down the system when the line connected to Super I/O for temperature over run is set. ; Check ExtEvent1 status.
14.9 Sleep Trap through SMI# This sample code provides an SMI# routine to develop some software workarounds or debugging functions before the system goes into ACPI sleep state. 14.9.1 Enable Sleep SMI# in ACPI ASL code The following example implements Sleep SMI Control Register enable by the ASL code _PTS method. Method(_PTS, 1) { Store(One, \_SB.PCI0.SMBS.SLPS) PTS(Arg0) Store(0, Index(WAKP,0)) // Clear Wake up package. Store(0, Index(WAKP,1)) // Clear Wake up package.
} PI1S,1, // PI0S,1, // Offset(0x55), SPRE,1, // Offset(0x68), ,3, TPDE,1, // ,1 //end of indexed field 14.9.2 Sleep Trap SMI Routine The following example implements the Sleep Trap SMI# routine.
SLPSMI_HANDLER_FAR ENDP ACPISleepTrapTable label byte dw offset cs:ACPISleepTrapS1 dw offset cs:ACPISleepTrapS2 dw offset cs:ACPISleepTrapS3 dw offset cs:ACPISleepTrapS4 dw offset cs:ACPISleepTrapS5 ACPISleepTrapS1 label byte dw offset cs:OemACPISleepTrapS1 dw 0FFFFh ACPISleepTrapS3 label byte dw offset cs:Port80_Enabled dw offset cs:OemACPISleepTrapS3 dw 0FFFFh ACPISleepTrapS4 label byte dw offset cs:OemACPISleepTrapS4 dw 0FFFFh ACPISleepTrapS5 label byte dw offset cs:OemACPISleepTrapS5 dw 0FFFFh 14.
pushad ; OEM specific CMOS setup option to Auto/Disable/enable HD Audio mov ax,CMOS_Azalia_Option ; OEM specific call ReadCMOSOption ; OEM specific cmp ax,1 ; Is it disable? je DisableAzaliaController ; Jump for Disable HD Audio ; OEMs may have a CMOS setup option for HD Audio clock source. ; The options may be USB 48 MHz or HD Audio 48 MHz ; Device 14h, function 2, register 43h, bit 0 = 1 for HD Audio clock.
mov call mov shr mov mov Byte PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \ +SB600_SMBUS_REGFC], 11111111b ; Set to GPIO ATI_fixed_delay_1ms_far ; Wait 1ms ecx, dword PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \ +SB600_SMBUS_REGFC] ecx,10h di,cx ; Save GPIO lines status at di[7:0] Byte PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \ +ATI_AZALIA_ExtBlk_DATA], 10101010b ; Set pin to HD Audio ; Interrupt routing table for HD Audio is at SMBUS ( Dev 14h, func 0) register 63h mo
not out al, BIT3 dx,al ; Clear bit 3 to disable HD Audio ; Output new data ; HD Audio port configuration through Extended registers. ; Extended registers are addressed as index/data through SMBUS(Dev 14h, func0) register 0F8h, ; and 0FCh ; Index 0 is Audio port configuration.
configure_Azalia_channel: call ATI_SB_Cfg_Azalia_Pin_CMD ; Configure this pin test_next_SDI: shr inc cmp je jmp ; Get next codec present ; Update the codec Channel number ; Completed all channels ; Yes, jump. Reset the controller and exit ; Do the next codec dl, 1 cl cl, 4 re_do_clear_reset test_SDI ; Reset the controller and wait till it enters reset state.
call ATI_SB_Cfg_Azalia_Delay ; About 30 uSec delay mov cmp jne eax, Dword PTR ES:[ebx+64h] eax, 010ec0880h ATI_SB_Cfg_Azalia_Pin_CMD_exit ; Immediate command input ; Is it Realtec codec? ; This routine works only with Realtec codec mov mov si, offset Azalia_Codec_Table_Start di, offset Azalia_Codec_Table_end ; Table end does not include front panel ; OEM may have a CMOS setup selection for Front panel audio (0=Auto, 1=Disable) mov call cmp je ax CMOS_Front_Panel ; OEM specific ReadCMOSOption ; OEM
jnz mov or mov test_again eax, cs:[si] eax, ecx Dword PTR ES:[ebx+60h], eax ; If bit 0 == 1, codec is not ready for command ; Get the command from the table ; Add codec number 0 to 3 ; Write immediate command call ATI_SB_Cfg_Azalia_Delay ; About 30 uSec delay add jmp si, 4 ; Update the pointer loop_Immediat_Command_Output_Interface ; Next command ATI_SB_Cfg_Azalia_Pin_CMD_exit: popad ret ATI_SB_Cfg_Azalia_Pin_CMD ENDP ;************************************************************************ : ATI_S
; * ; Delay for about 30 uSec * ; Input: None * ; * ;************************************************************************ ATI_fixed_delay_far PROC FAR push ax fixed_delay_1: in al, 61h test al, 00010000b jz fixed_delay_1 dec cx jz fixed_delay_2 fixed_delay_3: in al, 61h test al, 00010000b jnz fixed_delay_3 dec cx jnz fixed_delay_1 fixed_delay_2: pop ax ret ATI_fixed_delay ENDP ; refresh_port ; refresh_port Azalia_Codec_Table_Start: dd 01471C10h dd 01471D40h dd 01471E01h dd 01471F01h dd 01571C11h dd
dd 01a71E81h dd 01a71F01h dd 01b71C00h dd 01b71D00h dd 01b71E00h dd 01b71F40h dd 01c71C70h dd 01c71D10h dd 01c71E33h dd 01c71F99h dd 01d71C00h dd 01d71D10h dd 01d71E7fh dd 01d71F90h dd 01e71C50h dd 01e71D00h dd 01e71E44h dd 01e71F01h dd 01f71C60h dd 01f71D00h dd 01f71Ec4h dd 01f71F01h Azalia_Codec_Table_end: dd 01971C20h dd 01971D91h dd 01971E21h dd 01971F02h dd 01B71C40h dd 01B71D41h dd 01B71EA1h dd 01B71F02h Azalia_Codec_Table_FP_Enable_end: © 2008 Advanced Micro Devices Inc.
Appendix: Revision History Date Nov. 2008 Rev PDF 3.00 46157_sb600_bdg_pub_3.00 Description Initial public release. © 2008 Advanced Micro Devices Inc.
