Computer Hardware User's Manual

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AMD Sempron

Processor Model 10

with 256K L2 Cache

Data Sheet

Publication # 31994 Rev. A-1

Issue Date: August 2004

Summary of content (102 pages)

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AMD Sempron Processor Model 10 with 256K L2 Cache TM Data Sheet Publication # 31994 Rev.
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©2004 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 7.9 7.10 7.11 7.12 7.13 8 8.2 9.3 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . 44 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . 46 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . 73 Scan Pins . . . . .
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet vi 31994A —1 August 2004 Table of Contents
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 List of Figures Figure 1. Typical AMD Sempron™ Processor Model 10 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. AMD Sempron Processor Model 10 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet viii 31994A —1 August 2004 List of Figures
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 List of Tables Table 1. Electrical and Thermal Specifications for the AMD Sempron™ Processor Model 10 with 256K L2 Cache . . . . 21 Table 2. 333 FSB SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . 22 Table 3. 333 FSB AMD Athlon™ System Bus AC Characteristics . . . . . . 23 Table 4. 333 FSB AMD Athlon System Bus DC Characteristics . . . . . . . . 24 Table 5. Interface Signal Groupings . . . . . . . . . . .
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet x 31994A —1 August 2004 List of Tables
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Revision History Date Rev August 2004 A-1 Revision History Description ■ Initial release of the AMD Sempron™ Processor Model 10 Data Sheet xi
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet xii 31994A —1 August 2004 Revision History
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 1 Overview The AMD Sempron™ processor model 10 with 256K of L2 cache, the new value brand for every-day computing, performs at the top of its class. Using QuantiSpeed™ architecture, this processor is designed to power over 60,000 home and business applications, and it is compatible with various operating systems including Linux and all existing Windows® operating systems.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 The AMD Sempron processor model 10 with 256K of L2 cache is binary-compatible with existing x86 software and backwards compatible with applications optimized for MMX™, SSE, and 3 D N o w ! ™ t e ch n o l o gy.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 1.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Thermal Monitor 31994A —1 August 2004 AMD Sempron™ Processor Model 10 AMD Athlon™ System Bus AGP AGP Bus Memory Bus System Controller (Northbridge) SDRAM or DDR PCI Bus Peripheral Bus Controller (Southbridge) LAN SCSI Modem / Audio LPC Bus USB Dual EIDE BIOS Figure 1.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 2 Interface Signals This section describes the interface signals utilized by the AMD Sempron™ processor model 10. 2.1 Overview The AMD Athlon system bus architecture is designed to deliver excellent data movement bandwidth for next-generation x86 platforms as well as the high-performance required by enterprise-class application software.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 2.3 31994A —1 August 2004 Push-Pull (PP) Drivers The AMD Sempron processor model 10 supports push-pull (PP) drivers. The system logic configures the processor with the configuration parameter called SysPushPull (1=PP). The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins. See “ZN and ZP Pins” on page 75 for more information. 2.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor. This diagram shows the logical grouping of the input and output signals.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 8 Logic Symbol Diagram 31994A —1 August 2004 Chapter 3
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 4 Power Management This chapter describes the power management control system of the AMD Sempron™ Processor Model 10. The power management features of the processor are compliant with the ACPI 1.0b and ACPI 2.0 specifications. 4.1 Power Management States The AMD Sempron processor model 10 supports low-power Halt and Stop Grant states.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 The following sections provide an overview of the power m a n a g e m e n t s t a t e s . Fo r m o re d e t a i l s , re f e r t o t h e AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902. Note: In all power management states that the processor is powered, the system must not stop the system clock (SYSCLK/SYSCLK#) to the processor.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet must first connect the system bus. Connecting the system bus places the processor into the higher power probe state. After the Northbridge has completed all probes of the processor, the Northbridge must disconnect the AMD Athlon system bus again so that the processor can return to the low-power state.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 In C2, probes are allowed, as shown in Figure 3 on page 9 The Stop Grant state is also entered for the S1, Powered On Suspend, system sleep state based on a write to the SLP_TYP and SLP_EN fields in the ACPI-defined Power Management 1 control register in the Southbridge. During the S1 Sleep state, system software ensures no bus master or probe activity occurs.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet interrupt for Halt or STPCLK# deassertion. Reconnect is initiated by the Northbridge to probe the processor. The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Figure 4 shows STPCLK# assertion resulting in the processor in the St op Gra nt st ate and the A MD A thlon system bus disconnected. STPCLK# AMD Athlon™ System Bus Stop Grant CONNECT PROCRDY CLKFWDRST Stop Grant PCI Bus Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State An example of the AMD Athlon system bus disconnect sequence is as follows: 1.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state, connects the processor to the AMD Athlon system bus, and puts the processor into the Working state. Figure 5. Exiting the Stop Grant State and Bus Connect Sequence The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus: 1.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Connect State Diagram 31994A —1 August 2004 Figure 6 below and Figure 7 on page 17 show the Northbridge and processor connect state diagrams, respectively. . Condition Action 1 A disconnect is requested and probes are still pending. 2 A disconnect is requested and no probes are pending. A Deassert CONNECT eight SYSCLK periods after last SysDC sent. 3 A Connect special cycle from the processor. B Assert CLKFWDRST.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Connect 6/B 1 2/B Connect Pending 2 Disconnect Pending 5 Connect Pending 1 3/A Disconnect 4/C Condition 1 Action CONNECT is deasserted by the Northbridge (for a previously sent Halt or Stop Grant special cycle). Processor receives a wake-up event and must cancel 2 the disconnect request. 3 Deassert PROCRDY and slow down internal clocks. 4 Processor wake-up event or CONNECT asserted by Northbridge.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 4.3 31994A —1 August 2004 Clock Control The processor implements a Clock Control (CLK_Ctl) MSR (address C001_001Bh) that determines the internal clock divisor when the AMD Athlon system bus is disconnected. Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656, for more details on the CLK_Ctl register.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 5 CPUID Support AMD Sempron™ processor model 10 version and feature set recognition can be performed through the use of the CPUID instruction, that provides complete information about the processor—vendor, type, name, etc., and its capabilities. Software can make use of this information to accurately tune the system for maximum performance and benefit to users.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 20 CPUID Support 31994A —1 August 2004 Chapter 5
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 6 333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications This chapter describes the electrical specifications that are u n i q u e t o t h e a dva n c e d 3 3 3 f ro n t - s i d e b u s ( F S B ) AMD Sempron™ Processor Model 10 with 256K L2 cache. 6.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 6.2 31994A —1 August 2004 333 FSB AMD Sempron™ Processor Model 10 SYSCLK and SYSCLK# AC Characteristics Table 2 shows the SYSCLK/SYSCLK# differential clock AC characteristics of this processor. Table 2. 333 FSB SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes 50 166 MHz 1 30% 70% 2, 3 Clock Frequency Duty Cycle t1 Period 6 ns t2 High Time 1.0 ns t3 Low Time 1.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 6.3 333 FSB AMD Athlon™ System Bus AC Characteristics The AC characteristics of the AMD Athlon system bus of this processor are shown in Table 3. The parameters are grouped based on the source or destination of the signals involved. Table 3.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 6.4 31994A —1 August 2004 333 FSB AMD Athlon™ System Bus DC Characteristics Table 4 shows the DC characteristics of the AMD Athlon system bus for this processor. Table 4. 333 FSB AMD Athlon™ System Bus DC Characteristics Symbol VREF Parameter Condition Min Max (0.5 x VCC_CORE) (0.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 7 Electrical Data This chapter describes the electrical characteristics that apply to all desktop AMD Sempron™ processors model 10 with 256K L2 cache. 7.1 Conventions The conventions used in this chapter are as follows: ■ ■ 7.2 Current specified as being sourced by the processor is negative. Current specified as being sunk by the processor is positive.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 5.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 7.4 Frequency Identification (FID[3:0]) Table 7 shows the FID[3:0] DC characteristics. For more information, see “FID[3:0] Pins” on page 70. Table 7. FID[3:0] DC Characteristics Parameter IOL Description Min Output Current Low VOH Max 6 mA Output High Voltage 2.625 V 1 – | VOH – VCC_CORE | ≤ 1.60 V 2 Note: 1. The FID pins must not be pulled above 2.625 V, which is equal to 2.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 7.7 31994A —1 August 2004 VCC_CORE Characteristics Table 9 shows the AC and DC characteristics for VCC_CORE. See Figure 9 on page 29 for a graphical representation of the VCC_CORE waveform. Table 9.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Figure 9 shows the processor core voltage (V C C_C ORE ) waveform response to perturbation. The tMIN_AC (negative AC transient excursion time) and tMAX_AC (positive AC transient excursion time) represent the maximum allowable time below or above the DC tolerance thresholds. tmax_AC VCC_CORE_AC_MAX VCC_CORE_DC_MAX VCC_CORE_NOM VCC_CORE_DC_MIN VCC_CORE_AC_MIN tmin_AC ICORE_MAX dI /dt ICORE_MIN Figure 9.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 7.8 31994A —1 August 2004 Absolute Ratings The AMD Sempron processor model 10 should not be subjected to conditions exceeding the absolute ratings, as such conditions can adversely affect long-term reliability or result in functional damage. Table 10 lists the maximum absolute ratings of operation for the AMD Sempron processor model 10. Table 10. Absolute Ratings Parameter Description Min Max VCC_CORE Processor core voltage supply –0.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 7.9 SYSCLK and SYSCLK# DC Characteristics Table 11 shows the DC characteristics of the SYSCLK and SYSCLK# differential clocks. The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK# signal represents CLKIN# and RSTCLK# tied together. For more information about SYSCLK and SYSCLK#, see “SYSCLK and S Y S C L K # ” o n p a g e 7 3 a n d Ta b l e 1 9 , “ P i n N a m e Abbreviations,” on page 52.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 7.10 31994A —1 August 2004 General AC and DC Characteristics Table 12 shows the AMD Sempron processor model 10 AC and DC characteristics of the Southbridge, JTAG, test, and miscellaneous pins. Table 12.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 12. General AC and DC Characteristics (continued) Symbol Parameter Description Condition Min Max Units Notes TSU Sync Input Setup Time 2.0 ns 4, 5 THD Sync Input Hold Time 0.0 ps 4, 5 TDELAY Output Delay with respect to RSTCLK 0.0 ns 5 TBIT Input Time to Acquire 20.0 ns 7, 8 TRPT Input Time to Reacquire 40.0 ns 9–13 TRISE Signal Rise Time 1.0 3.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 7.11 31994A —1 August 2004 Open Drain Test Circuit Figure 11 is a test circuit that may be used on automated test equipment (ATE) to test for validity on open-drain pins. Refer to Table 12, “General AC and DC Characteristics,” on page 32 for timing requirements. VTermination1 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Notes: 1. VTermination = 1.2 V for VID and FID pins VTermination = 1.0 V for APIC pins 2.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 7.12 Thermal Diode Characteristics The AMD Sempron processor model 10 provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor. The diode anode (THERMDA) and cathode (THERMDC) are available as pins on the processor, as described in “THERMDA and THERMDC Pins” on page 73.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Thermal Protection Characterization 31994A —1 August 2004 The following section describes parameters relating to thermal protection. The implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement. Thermal limits in motherboard design are necessary to protect the processor from thermal damage.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 14 shows the TSHUTDOWN and TSD_DELAY specifications for circuitry in motherboard design necessary for thermal protection of the processor. Table 14.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 15. APIC Pin AC and DC Characteristics (continued) Symbol Parameter Description Condition Min Max Units Notes TRISE Signal Rise Time 1.0 3.0 V/ns 3 TFALL Signal Fall Time 1.0 3.0 V/ns 3 TSU Setup Time 1 ns THD Hold Time 1 ns CPIN Pin Capacitance 4 12 pF Notes: 1. Characterized across DC supply voltage range. 2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent. 3.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 8 Signal and Power-Up Requirements The AMD Sempron™ processor model 10 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges. 8.1 Power-Up Requirements Signal Sequence and Timing Description Figure 12 shows the relationship between key signals in the system during a power-up sequence. This figure details the requirements of the processor.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Power-Up Timing Requirements. The signal timing requirements are as follows: 1. RESET# must be asserted before PWROK is asserted. The AMD Sempron processor model 10 does not set the correct clock multiplier if PWROK is asserted prior to a RESET# assertion. It is recommended that RESET# be asserted at least 10 nanoseconds prior to the assertion of PWROK.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet clock must be valid at this time. The system clocks are designed to be running after 3.3 V has been within specification for three milliseconds. 4. PWROK assertion to deassertion of RESET# The duration of RESET# assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1 ns phase error.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Clock Multiplier Selection (FID[3:0]) 31994A —1 August 2004 The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to determine the correct serial initialization packet (SIP). The chipset then sends the SIP information to the processor for configuration of the AMD Athlon system bus for the clock multiplier that determines the processor frequency indicated by the FID[3:0] code.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 9 Mechanical Data Th e A MD S e m p ron ™ p roc es s o r m o d e l 10 c o n ne c t s t o themotherboard through a Pin Grid Array (PGA) socket named Socket A. This processor utilizes the Organic Pin Grid Array (OPGA) package type described in this chapter. For more information, see the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363. 9.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 9.2 31994A —1 August 2004 AMD Sempron™ Processor Model 10 Part Number 27488 OPGA Package Dimensions Table 17 shows the part number 27488 OPGA package dimensions in millimeters assigned to the letters and symbols used in the 27488 package diagram, Figure 13 on page 45. Table 17. Dimensions for the AMD Sempron™ Processor Model 10 Part Number 27488 OPGA Package Letter or Symbol D/E Minimum Maximum Dimension1 Dimension1 49.27 49.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Figure 13.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 9.3 31994A —1 August 2004 AMD Sempron™ Processor Model 10 Part Number 27493 OPGA Package Dimensions Table 18 shows the part number 27493 OPGA package dimensions in millimeters assigned to the letters and symbols shown in the 27493 package diagram, Figure 14 on page 47. Table 18. Dimensions for the AMD Sempron™ Processor Model 10 Part Number 27493 OPGA Package Letter or Symbol D/E Minimum Maximum Dimension1 Dimension1 49.27 49.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Figure 14.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 48 Mechanical Data 31994A —1 August 2004 Chapter 9
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31994A —1 August 2004 10 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Pin Descriptions This chapter includes pin diagrams of the organic pin grid array (OPGA) for the AMD Sempron™ processor model 10, a listing of pin name abbreviations, and a cross-referenced listing of pin locations to signal names. 10.1 Pin Diagram and Pin Name Abbreviations Figure 15 on page 50 shows the staggered Pin Grid Array (PGA) for the AMD Sempron™ processor model 10.
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50 Pin Descriptions Z X V T R P AN AM AL AK AJ AH AG AF AE AD AC AB AA Y K H F D B M W U S Q N L J G E C A 1 INTR IGNNE# FERR A20M# STPC# DBRDY FID[2] FID[0] TDI SCNCK1 TCK PICCLK VID[0] SAO#0 SAO#10 SAO#11 SAO#7 1 2 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS 2 3 3 NMI FLUSH# INIT# RESET# PWROK PLTST# DBREQ# FID[3] FID[1] TRST# SCNINV TMS PICD#0 VID[1] SAO#1 SAO#14 SAOC# SAO#9 SAO#1
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Chapter 10 8 6 4 2 10 Pin Descriptions 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 5 3 1 C C A SD#41 SD#42 SD#43 SD#45 SD#38 SD#47 SD#37 SD#56 SD#59 SD#60 SD#51 NC SDOC#3 SD#54 SAO#2 SAO#8 SAO#9 SAO#7 SDOC#1 B VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS B SD#30 SD#40 SDOC#2 NC SD#44 SD#34 SD#35 SD#39 SD#57 NC SD#62 SD#63 SD#53 SD#61 SD#55 SAO#3
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 19. Pin Name Abbreviations Abbreviation 31994A —1 August 2004 Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 19. Pin Name Abbreviations (continued) Abbreviation Chapter 10 Full Name Pin Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 19. Pin Name Abbreviations (continued) Abbreviation Full Name Pin 31994A —1 August 2004 Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 19. Pin Name Abbreviations (continued) Abbreviation Full Name Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 19. Pin Name Abbreviations (continued) Abbreviation VCC Full Name VCC_CORE Pin F24 VCC VCC_CORE VCC 31994A —1 August 2004 Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 19. Pin Name Abbreviations (continued) Abbreviation VCC Full Name VCC_CORE Pin AK34 VCC VCC_CORE VCC Table 19.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 19. Pin Name Abbreviations (continued) Abbreviation 58 Full Name Pin 31994A —1 August 2004 Table 19.
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31994A —1 August 2004 10.2 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Pin List Table 20 on page 60 cross-references Socket A pin location to signal name. The “L” (Level) column shows the electrical specification for this pin. “P” indicates a push-pull mode driven by a single source. “O” indicates open-drain mode that allows devices to share the pin. Note: The AMD Sempron processor supports push-pull drivers. For more information, see “Push-Pull (PP) Drivers” on page 6.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table 20. Cross-Reference by Pin Location Pin Name 31994A —1 August 2004 Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued) Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 20. Cross-Reference by Pin Location (continued)Table 20.
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31994A —1 August 2004 10.3 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Detailed Pin Descriptions The information in this section pertains to Table 20 on page 60. A20M# Pin A20M# is an input from the system used to simulate address wrap-around in the 20-bit 8086. AMD Pin AMD Socket A processors do not implement a pin at location AH6. All Socket A designs must have a top plate or cover that blocks this pin location. When the cover plate blocks this location, a non-AMD part (e.g.
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31994A —1 August 2004 CLKIN, RSTCLK (SYSCLK) Pins AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Connect CLKIN with RSTCLK and name it SYSCLK. Connect CLKIN# with RSTCLK# and name it SYSCLK#. Length match the clocks from the clock generator to the Northbridge and processor. See “SYSCLK and SYSCLK#” on page 73 for more information. CONNECT Pin CONNECT is an input from the system used for power management and clock-forward initialization at reset.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet FID[3:0] Pins 31994A —1 August 2004 FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the 4-bit processor clock-to-SYSCLK ratio. Table 21 describes the encodings of the clock multipliers on FID[3:0]. Table 21. FID[3:0] Clock Multiplier Encodings FID[3:0]2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Processor Clock to SYSCLK Frequency Ratio 11 11.5 12 ≥ 12.51 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet signals High above 2.5 V. Do not expose these pins to a differential voltage greater than 1.60 V, relative to the processor core voltage. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor Motherboard Design Guide, order# 24363 for the required supporting circuitry.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 INTR Pin INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. JTAG Pins TCK, TMS, TDI, TRST#, and TDO are the JTAG interface. Connect these pins directly to the motherboard debug connector. Pull TDI, TCK, TMS, and TRST# up to VCC_CORE with pullup resistors.
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31994A —1 August 2004 PWROK Pin AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. For more information, Chapter 8, “Signal and Power-Up Requirements” on page 39. SADDIN[1:0]# and SADDOUT[1:0]# Pins The AMD Sempron processor model 10 does not support SADDIN[1:0]# or SADDOUT[1:0]#.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet VID[4:0] Pins 31994A —1 August 2004 The VID[4:0] (Voltage Identification) outputs are used to dictate the V CC_CORE voltage level. The VID[4:0] pins are strapped to ground or left unconnected on the processor package. The VID[4:0] pins are pulled up on the motherboard and used by the VCC_CORE DC/DC converter. The VID codes and corresponding voltage levels are shown in Table 23. Table 23.
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31994A —1 August 2004 ZN and ZP Pins Chapter 10 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet ZN (AC5) and ZP (AE5) are the push-pull compensation circuit pins. In Push-Pull mode (selected by the SIP parameter SysPushPull asserted), ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedance Z 0 of the transmission line. ZP is tied to VSS with a resistor that has a resistance matching the impedance Z0 of the transmission line.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 76 Pin Descriptions 31994A —1 August 2004 Chapter 10
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31994A —1 August 2004 11 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Ordering Information Standard AMD Sempron™ Processor Model 10 Products AMD standard products are available in several operating ranges. The ordering part numbers (OPN) are formed by a combination of the elements, as shown in Figure 17. OPN1 SD C 2800 D U T 3 D Advanced Front-Side Bus: D = 333 Size of L2 Cache: 3 = 256 Kbytes Die Temperature: T = 90°C Operating Voltage: U = 1.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 78 Ordering Information 31994A —1 August 2004 Chapter 11
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Appendix A Thermal Diode Calculations This section contains information about the calculations for the on-die thermal diode of the AMD Sempron™ processor model 10. For electrical information about this thermal diode, see Table 13, “Thermal Diode Electrical Characteristics,” on page 35. Ideal Diode Equation The ideal diode equation uses the variables and constants defined in Table 24. Table 24.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Equation (1) shows the ideal diode calculation. k I V BE = n f, lumped ⋅ --- ⋅ T ⋅ ln ⎛⎝ ---C-⎞⎠ IS q (1) Sourcing two currents and using Equation (1) derives the difference in the base-to-emitter voltage that leads to finding the diode temperature as shown in Equation (2).
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31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet The formulas in Equation (3) and Equation (4) can be used to calculate the temperature offset for temperature sensors that do not employ series resistance cancellation. The result is added to the value measured by the temperature sensor. Contact the vendor of the temperature sensor being used for the value of nf,TS. Refer to the document, On-Die Thermal Diode Characterization, order# 25443, for further details.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 82 31994A —1 August 2004 Appendix A - Thermal Diode Calculations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Appendix B Conventions and Abbreviations This section contains information about the conventions and abbreviations used in this document. Signals and Bits ■ ■ ■ ■ ■ Active-Low Signals — Signal names containing a pound sign, such as SFILL#, indicate active-Low signals. They are asserted in their Low-voltage state and negated in their High-voltage state.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Data Terminology The following list defines data terminology: ■ ■ ■ ■ ■ ■ ■ 84 Quantities • A word is two bytes (16 bits) • A doubleword is four bytes (32 bits) • A quadword is eight bytes (64 bits) Addressing—Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Abbreviations and Acronyms Table 26 contains the definitions of abbreviations used in this document. Table 26.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 26. Abbreviations (continued) Abbreviation Meaning pF picofarad pH picohenry ps picosecond s Second V Volt W Watt Table 27 contains the definitions of acronyms used in this document. Table 27.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 27.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Table 27.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004 Related Publications These documents provide helpful information about the AMD Sempron™ processor model 10, and can be found with o t h e r re l a t e d d o c u m e n t s a t t h e A M D We b s i t e , http://www.amd.com.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 90 31994A —1 August 2004 Appendix B - Conventions and Abbreviations