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Revision Guide for

AMD Family 10h

Processors

41322Publication # 3.84 Revision:

August 2011Issue Date:

Summary of content (147 pages)

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Revision Guide for AMD Family 10h Processors Publication # 41322 Revision: 3.
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© 2006-2011 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 Revision History Date Revision Description August 2011 3.84 Clarified erratum #406; Added errata #625, #643, #669 and #670; Updated erratum #400 and #610 and MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) due to the addition of erratum #669. February 2011 3.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 Date Revision Description January 2010 3.66 Added AMD Athlon™ Processor to Tables 7 and 28; Updated Table 8; Updated Constructing the Processor Name String; Added BL-C3 and DAC3 silicon information to Tables 8, 26 and 27; Added erratum #383 and updated MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) and MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) for OSVW[3]; Added errata #408 and #437. December 2009 3.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 Date Revision Description November 2008 3.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors Overview The purpose of the Revision Guide for AMD Family 10h Processors is to communicate updated product information to designers of computer systems and software developers.
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41322 • • • • • • • • • • • • • • • Rev. 3.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 Conventions Numbering • Binary numbers. Binary numbers are indicated by appending a “b” at the end, e.g., 0110b. • Decimal numbers. Unless specified otherwise, all numbers are decimal. This rule does not apply to the register mnemonics. • Hexadecimal numbers. Hexadecimal numbers are indicated by appending an “h” to the end, e.g., 45F8h. • Underscores in numbers.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 • APICXXX: APIC memory-mapped registers; XXX is the byte address offset from the base address in hex (this may be 2 or 3 digits). The base address for this space is specified by the APIC Base Address Register (APIC_BAR) at MSR0000_001B. • CPUID FnXXXX_XXXX_RRR_xYYY: processor capability information returned by the CPUID instruction where the CPUID function is XXXX_XXXX (in hex) and the ECX input is YYY (if specified).
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Revision Guide for AMD Family 10h Processors Table 1. August 2011 Arithmetic and Logic Operators (Continued) Operator 10 41322 Rev. 3.84 Definition << Shift left first operand by the number of bits specified by the 2nd operand. E.g. (01b << 01b == 10b). >> Shift right first operand by the number of bits specified by the 2nd operand. E.g. (10b >> 01b == 01b).
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 Processor Identification This section shows how to determine the processor revision, program and display the processor name string, and construct the processor name string. Revision Determination A processor revision is identified using a unique value that is returned in the EAX register after executing the CPUID instruction function 0000_0001h (CPUID Fn0000_0001_EAX).
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Revision Guide for AMD Family 10h Processors CPUID Fn0000_0001_EAX (Mnemonic) Embedded AMD Opteron™ Processor CPUID Values for AMD Family 10h Fr5 (1207) Processor Revisions Quad-Core AMD Opteron™ Processor 00100F42h (RB-C2) X X CPUID Fn0000_0001_EAX (Mnemonic) Embedded AMD Opteron™ Processor CPUID Values for AMD Family 10h Fr6 (1207) Processor Revisions Six-Core AMD Opteron™ Processor 00100F80h (HY-D0) X X CPUID Fn0000_0001_EAX (Mnemonic) Embedded AMD Opteron™ Processor CPUID Values for AMD F
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Rev. 3.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 Mixed Processor Revision Support AMD Family 10h processors with different revisions can be mixed in a multiprocessor system. Mixed revision support includes the AMD Opteron™ processor configurations as shown in Table 12. Processors of different package types can not be mixed in a multiprocessor system. Processor Revision DR-B2 DR-B3 RB-C2 HY-D0 HY-D1 Supported Mixed Revision Configurations DR-BA Table 12.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors Programming and Displaying the Processor Name String This section, intended for BIOS programmers, describes how to program and display the 48-character processor name string that is returned by CPUID Fn8000_000[4:2].
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 • PkgType[3:0] is from CPUID Fn8000_0001_EBX[31:28]. This field specifies the package type as defined in the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order# 31116, and is used to index the appropriate string tables from Table 13.
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41322 Rev. 3.84 Table 14.
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Revision Guide for AMD Family 10h Processors Table 15. 41322 Rev. 3.84 String2 Values for Fr2, Fr5 and Fr6 (1207) Processors Pg[0] NC [7:0] String2 [3:0] 0b 03h Ah SE 1 Bh HE 1 Ch EE 1 0h SE 1 1h HE 1 2h EE 1 05h 1b Value Note xxh Fh 03h 1h GF HE - 2h HF HE - 3h VS - 4h QS HE - 5h NP HE - 6h KH HE - 7h KS EE - 1h QS - 2h KS HE - Reserved - 05h All other values 2 Notes: 1. The string includes a space as the leading character. 2.
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41322 Rev. 3.84 Table 16.
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Revision Guide for AMD Family 10h Processors Table 16. 41322 Rev. 3.
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41322 Rev. 3.84 Table 17.
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Revision Guide for AMD Family 10h Processors Table 17. 41322 Rev. 3.84 August 2011 String2 Values for AM2r2 and AM3 Processors (Continued) Pg[0] NC [7:0] String2 [3:0] 1b 01h 1h L Processor - 2h C Processor - 1h L Processor - 4h T Processor - Reserved - 03h All other values Value Note Description Notes: 1. The string includes a space as the leading character. 2. The String2 index 0Fh is defined as an empty string, i.e., no suffix. Table 18.
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41322 Rev. 3.84 Table 19. Revision Guide for AMD Family 10h Processors August 2011 String2 Values for S1g3 and S1g4 Processors Pg[0] NC [7:0] String2 [3:0] 0b 00h 1h 0 Processor - 01h 2h 0 Dual-Core Processor - 02h 2h 0 Triple-Core Processor - 03h 1h 0 Quad-Core Processor - xxh Fh All other values Value Note Description 1 Reserved - Notes: 1. The String2 index 0Fh is defined as an empty string, i.e., no suffix. Table 20.
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Revision Guide for AMD Family 10h Processors Table 22. 41322 Rev. 3.84 String1 Values for ASB2 Processors Pg[0] NC [7:0] String1 [3:0] 0b 0b 1b AMD Athlon(tm) II Neo K - 2b AMD V - 3b AMD Athlon(tm) II Neo R - 1b AMD Turion(tm) II Neo K - 2b AMD Athlon(tm) II Neo K - 3b AMD V - 4b AMD Turion(tm) II Neo N - 5b AMD Athlon(tm) II Neo N - AMD Processor Model Unknown - 1b All other values Table 23.
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41322 Rev. 3.84 Table 25. Revision Guide for AMD Family 10h Processors August 2011 String2 Values for C32r1 Processors Pg[0] NC [7:0] String2 [3:0] 0b 3h 0h HE 1 1h EE 1 0h HE 1 1h EE 1 5h 1b Value Note xxh Fh 3h 1h QS HE - 2h LE HE - 3h CL EE - 1h KX HE - 2h GL EE - Reserved - 5h All other values Description 2 Notes: 1. The string includes a space as the leading character. 2. The String2 index 0Fh is defined as an empty string, i.e., no suffix.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 F4x164 Fixed Errata Register Communicating the status of an erratum within a stepping of a processor family is necessary in certain circumstances. F4x164 is used to communicate the status of such an erratum fix so that BIOS or system software can determine the necessity of applying the workaround.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System Programming, order# 24593, is used to specify the number of valid status bits within the OS Visible Work-around status registers. The reset default value of this register is 0000_0000_0000_0000h. BIOS shall program the OSVW_ID_Length to 0004h prior to hand-off to the OS.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System Programming, order# 24593, provides the status of the known OS visible errata. Known errata are assigned an OSVW_ID corresponding to the bit position within the valid status field. Operating system software should use MSRC001_0140 to determine the valid length of the bit status field.
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41322 Rev. 3.84 Table 26.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 Product Errata This section documents product errata for the processors. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 27 cross-references the revisions of the part to each erratum. An “X” indicates that the erratum applies to the revision.
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41322 Rev. 3.84 Table 27.
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Revision Guide for AMD Family 10h Processors Table 27. 41322 Rev. 3.84 August 2011 Cross-Reference of Product Revision to Errata (Continued) Revision Number DR-B2 DR-B3 RB-C2 BL-C2 DA-C2 RB-C3 BL-C3 DA-C3 HY-D0 HY-D1 PH-E0 Errata Description DR-BA No.
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41322 Rev. 3.84 Table 27. Revision Guide for AMD Family 10h Processors August 2011 Cross-Reference of Product Revision to Errata (Continued) VLDT Maximum Current Specification Exceeded at HyperTransport™ Link Transfer Rates Up to 2.0 GT/s 397 RB-C3 DA-C2 BL-C2 RB-C2 PH-E0 396 HY-D1 Incorrect Data Masking in Ganged DRAM Mode HY-D0 395 DA-C3 Performance Monitor May Count Fastpath Double Operation Instructions Incorrectly BL-C3 393 DR-B3 Errata Description DR-BA No.
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Revision Guide for AMD Family 10h Processors Table 27. 41322 Rev. 3.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 Tables 28-29 cross-reference the errata to each processor segment. An empty cell signifies that the erratum does not apply to the processor segment. “X” signifies that the erratum applies to the processor segment. “N/A” signifies that the erratum does not apply to the processor segment due to the processor revision.
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Revision Guide for AMD Family 10h Processors AMD Opteron™ 6100 Series Processor and Embedded AMD Opteron™ Processor in a G34r1 Package AMD Phenom™ Triple-Core and Quad-Core Processors AMD Athlon™ Dual-Core Processor AMD Phenom™ II X6 Processor AMD Athlon™ II Processor AMD Athlon™ II X2 and AMD Athlon™ XL and XLT Processors AMD Sempron™ Processor AMD Sempron™ X2 Processor N/A N/A N/A X X X X N/A X X X X X X X X 328 X N/A N/A N/A X X N/A N/A N/A N/A N/A N/A N/A 336 X N
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Revision Guide for AMD Family 10h Processors AMD Athlon™ II Neo Mobile Processor AMD Athlon™ II Dual-Core Mobile Processor AMD Athlon™ II Neo Dual-Core Mobile Processor AMD Phenom™ II Dual-Core, Triple-Core and Quad-Core Mobile Processors AMD Turion™ II Dual-Core Mobile Processor AMD Turion™ II Neo Dual-Core Mobile Processor AMD Turion™ II Ultra, Dual-Core Mobile Processor AMD Sempron™ Mobile Processor AMD V-Series Mobile Processor AMD V-Series Dual-Core Mobile Processor Cross-Reference of Errata
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41322 Rev. 3.
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Revision Guide for AMD Family 10h Processors AMD Athlon™ II Neo Mobile Processor AMD Athlon™ II Dual-Core Mobile Processor AMD Athlon™ II Neo Dual-Core Mobile Processor AMD Phenom™ II Dual-Core, Triple-Core and Quad-Core Mobile Processors AMD Turion™ II Dual-Core Mobile Processor AMD Turion™ II Neo Dual-Core Mobile Processor AMD Turion™ II Ultra, Dual-Core Mobile Processor AMD Sempron™ Mobile Processor AMD V-Series Mobile Processor AMD V-Series Dual-Core Mobile Processor 400 X X X X X X X
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322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 Table 30 cross-references the errata to each package type. An empty cell signifies that the erratum does not apply to the package type. “X” signifies that the erratum applies to the package type. “N/A” signifies that the erratum does not apply to the package type due to the processor revision.
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Revision Guide for AMD Family 10h Processors Fr5 (1207) Fr6 (1207) G34r1 C32r1 AM2r2 AM3 ASB2 S1g3 S1g4 Cross-Reference of Errata to Package Type (Continued) Fr2 (1207) Table 30. 41322 Rev. 3.
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Rev. 3.84 X X 408 411 414 S1g4 X S1g3 X X ASB2 X 407 AM3 406 AM2r2 C32r1 G34r1 Fr6 (1207) Errata Number Cross-Reference of Errata to Package Type (Continued) Fr5 (1207) Table 30.
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Revision Guide for AMD Family 10h Processors 57 41322 Rev. 3.84 August 2011 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors Description In some cases, the machine check error code on a data cache (DC) tag array parity error erroneously classifies an eviction error as a snoop error. The common cases of cache line replacements and external probes are classified correctly (as eviction and snoop respectively).
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41322 60 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors Single Machine Check Error May Report Overflow Description A single parity error encountered in the data cache tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the DC Machine Check Status register (bit 62 of MSR0000_0401). Potential Effect on System System software may be informed of a machine check overflow when only a single error was actually encountered.
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Revision Guide for AMD Family 10h Processors 77 41322 Rev. 3.84 August 2011 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit Description If the target selector of a far call or far jump (CALLF or JMPF) instruction references a 16-byte long mode system descriptor where any of the last 8 bytes are beyond the GDT or LDT limit, the processor fails to report a General Protection fault.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 178 Default RdPtrInit Value Does Not Provide Sufficient Timing Margin Description Insufficient separation of the read pointer and write pointer in the synchronization FIFO can lead to setup violations in the transmit FIFO. Potential Effect on System The setup violations may lead to data corruption. Suggested Workaround BIOS should program F2x[1, 0]78[3:0] (RdPtrInit) to 5h.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 244 A DIV Instruction Followed Closely By Other Divide Instructions May Yield Incorrect Results Description A DIV instruction with a dividend less than 64 that is followed in close proximity by a DIV, IDIV, or AAM instruction may produce incorrect results. Potential Effect on System Possible data corruption. Suggested Workaround Contact your AMD representative for information on a BIOS update.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 248 INVLPGA of A Guest Page May Not Invalidate Splintered Pages Description When an address mapped by a guest uses a larger page size than the host, the TLB entry created uses the size of the smaller page; this is referred to as page splintering. TLB entries that are the result of page splintering may not be invalidated when the large page is invalidated in the guest using INVLPGA.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 254 Internal Resource Livelock Involving Cached TLB Reload Description Under a highly specific and detailed set of conditions, an internal resource livelock may occur between a TLB reload and other cached operations. Potential Effect on System The system may hang. Suggested Workaround BIOS should set MSRC001_1023[21] to 1b.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 260 REP MOVS Instruction May Corrupt Source Address Description The processor may corrupt the source address for REP MOVS instructions using 16- or 32-bit addressing when a fault occurs on the first iteration and ECX is greater than 255 and EDI equals 0. Potential Effect on System Unpredictable system behavior. Suggested Workaround Contact your AMD representative for information on a BIOS update.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 261 Processor May Stall Entering Stop-Grant Due to Pending Data Cache Scrub Description The processor may stall if a correctable error is identified by the data cache scrubber within a small window of time before the processor enters a stop-grant state when another scrub is pending. Potential Effect on System The system may hang. Suggested Workaround BIOS should set MSRC001_1022[24].
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 263 Incompatibility With Some DIMMs Due to DQS Duty Cycle Distortion Description Some DIMMs exhibit a duty cycle distortion on the first DQS pulse of an incoming read request which may cause the processor's DRAM interface to miss a beat of data in a read burst. Potential Effect on System Undefined system behavior due to incorrect read data.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 264 Incorrect DRAM Data Masks Asserted When DRAM Controller Data Interleaving Is Enabled Description The processor may incorrectly assert the DRAM data masks for writes less than a cache line when DRAM controller data interleaving is enabled. Potential Effect on System Data corruption. Suggested Workaround BIOS should set MSRC001_001F[36] (DisDatMsk) to 1b when F2x110[5] (DctDatIntLv) is set to 1b.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 269 ITT Specification Exceeded During Power-Up Sequencing Description Processor current consumption may exceed the ITT maximum specified for C0/S0 operation if the VTT voltage regulator is enabled before the VDDIO voltage regulator and the VDDIO regulator enables a low resistance path to VSS while VTT - VDDIO > 400 mV. Potential Effect on System The VTT voltage regulator may shut down if ITT exceeds the platform design limit.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 274 IDDIO Specification Exceeded During Power-Up Sequencing Description Processor current consumption may exceed the IDDIO maximum specified for C0/S0 operation during power-up sequencing. Potential Effect on System None expected if the VDDIO voltage regulator is sourced by a RUN (running) plane from the power supply during power-up sequencing.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 278 Incorrect Memory Controller Operation In Ganged Mode Description The DRAM controller 0 (DCT0) and DRAM controller 1 (DCT1) refresh counters may not be initialized to the same value using hardware controlled DRAM initialization when operating in ganged mode. Potential Effect on System Incorrect memory controller operation.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 279 HyperTransport™ Link RTT and RON Specification Violations Description The RTT and RON specifications for the HyperTransport™ link may be violated on some processor revisions. Potential Effect on System These violations do not result in any other HyperTransport™ link electrical specification violations. There are no known functional failures related to this problem. Suggested Workaround None required.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 280 Time Stamp Counter May Yield An Incorrect Value Description Reads of the time stamp counter may yield an inconsistent result. Potential Effect on System Undefined behavior for software that relies on a continuously increasing time stamp counter value. Suggested Workaround Contact your AMD representative for information on a BIOS upgrade.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 293 Memory Instability After PWROK Assertion Description The DRAM DQS DLL may not lock properly after PWROK is asserted. Potential Effect on System The system may have degraded memory margins leading to unreliable DRAM signaling. In some circumstances, this may cause BIOS to degrade the memory speed.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 295 DRAM Phy Configuration Access Failures Description Under a highly specific set of asynchronous timing conditions established during cold boot (S5 to S0 transition) or resume (S4 or S3 to S0 transition), the skew between the DRAM controllers (DCTs) and DRAM phy may lead to unreliable communication for DRAM phy configuration accesses.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 297 Single Machine Check Error May Report Overflow Description A single tag snoop parity error encountered in the instruction cache tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the IC Machine Check Status register (MSR0000_0405[62]). Potential Effect on System System software may be informed of a machine check overflow when only a single error was actually encountered.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 298 L2 Eviction May Occur During Processor Operation To Set Accessed or Dirty Bit Description The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 300 Hardware Memory Clear Is Not Supported After Software DRAM Initialization Description When using software-controlled DRAM device initialization using EnDramInit (F2x[1, 0]7C DRAM Initialization Register[31]), hardware memory clear using MemClrInit (F2x110 DRAM Controller Select Low Register[3]) does not function.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 301 Performance Counters Do Not Accurately Count MFENCE or SFENCE Instructions Description MFENCE and SFENCE instructions are not accurately counted by the performance monitor when MSRC001_000[3:0][7:0] (EventSelect) is 1D4h, or 1D5h. Potential Effect on System Performance monitoring software will not be able to count MFENCE and SFENCE instructions. Suggested Workaround None.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 302 MWAIT Power Savings May Not Be Realized when Two or More Cores Monitor the Same Address Description Execution of the MONITOR instruction may cause another core to exit the monitor event pending state. Potential Effect on System No functional impact; however, the power savings associated with the MWAIT instruction may not be realized. Suggested Workaround Contact your AMD representative for information on a BIOS update.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 308 Processor Stall in C1 Low Power State Description Under a highly specific set of internal timing conditions, an L3 eviction may stall for a processor core that has entered the C1 (halt) state. If the processor core has already entered the low power state and the CpuPrbEn bit in the C1 SMAF is 0b (F3x84[24]), the stall persists until the processor core comes out of the low power state.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 309 Processor Core May Execute Incorrect Instructions on Concurrent L2 and Northbridge Response Description Under a specific set of internal timing conditions, an instruction fetch may receive responses from the L2 and the northbridge concurrently. When this occurs, the processor core may execute incorrect instructions. Potential Effect on System Unpredictable system behavior. Suggested Workaround BIOS should set MSRC001_1023[23].
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 315 FST and FSTP Instructions May Calculate Operand Address in Incorrect Mode Description A Floating-Point Store Stack Top (FST or FSTP) instruction in 64-bit mode that is followed shortly by an instruction that changes to compatibility mode may incorrectly calculate the operand address using compatibility mode.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 319 Inaccurate Temperature Measurement Description The internal thermal sensor used for CurTmp (F3xA4[31:21]), hardware thermal control (HTC), software thermal control (STC) thermal zone, and the sideband temperature sensor interface (SB-TSI) may report inconsistent values.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 322 Address and Command Fine Delay Values May Be Incorrect Description The DRAM phy uses the memory speed at the time of DRAM initialization or self-refresh exit to adjust the fine delay values based on internal DLL settings. Data written to fine delay registers prior to DRAM initialization or self-refresh exit may be adjusted incorrectly.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 326 Misaligned Load Operation May Cause Processor Core Hang Description Under a highly specific set of internal timing conditions, load operations with a misaligned operand may hang. Any instruction loading data from memory without a LOCK prefix where the first byte and the last byte are in separate octal words may cause the condition mentioned above. Potential Effect on System Processor core hang.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 327 HyperTransport™ Link RTT Specification Violation Description The RTT specification for the HyperTransport™ link may be violated on some processor revisions. Potential Effect on System These violations do not result in any other HyperTransport™ link electrical specification violations. There are no known functional failures related to this problem.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 328 BIST May Report Failures on Initial Powerup Description When BIST is run after initial powerup, a non-zero (i.e., failing) value may be erroneously reported in EAX. Subsequent BIST runs (induced by warm resets) are not affected by this erratum, and accurately report pass/fail as determined by the presence or absence of detectable defects in the structures tested.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 336 Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling (IBS) is enabled in the following cases: • • The IBS may not tag an operation when the current counter in IBS Execution Control Register[IbsOpCurCnt] (MSRC001_1033[51:32]) reaches the value in IBS Fetch Control Register[IbsOpMaxCnt] (MSRC001_1030[15:0], resulting in a missed sample.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 338 Northbridge Instruction-Based Sampling Fields May Be Inaccurate Description The IBS Op Data 2 Register[NbIbsReqDstProc] (MSRC001_1036[4]) may be incorrect when the northbridge is performing back-to-back operations while an instruction tagged for Instruction-Based Sampling (IBS) is executed and IBS Op Data 2 Register[NbIbsReqSrc] (MSRC001_1036[2:0]) is 011b or 111b.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 339 APIC Timer Rollover May Be Delayed Description The APIC timer does not immediately rollover when it transitions to zero and Timer Local Vector Table Entry[Mode] (APIC320[17]) is configured to run in periodic mode. In addition, when Timer Local Vector Table Entry[Mask] (APIC320[16]) is configured to generate an interrupt, the interrupt is also delayed whether configured for periodic or one-shot mode.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 342 SMIs That Are Not Intercepted May Disable Interrupts Description During a resume from SMM that is due to an unintercepted SMI from a SVM guest context, the processor core does not restore the correct effective interrupt flag (IF) if the guest VMCB V_INTR_MASKING bit (offset 060h bit 24) is 1b. Under these circumstances, the effective interrupt flag may be zero.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 343 Eviction May Occur When Using L2 Cache as General Storage During Boot Description When system software is using the L2 cache as general storage before memory initialization, the processor may determine during speculative execution that data destined for the instruction cache is dirty. The processor will then evict these cache lines, resulting in lost data.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 344 Intermittent HyperTransport™ Link Training Failures Description The HyperTransport™ link training may fail at speeds greater than 2.0 GT/s. Potential Effect on System When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 346 System May Hang if Core Frequency is Even Divisor of Northbridge Clock Description When one processor core is operating at a clock frequency that is higher than the northbridge clock frequency, and another processor core is operating at a clock frequency that is an even divisor of the northbridge clock frequency, the northbridge may fail to complete a cache probe. Potential Effect on System System hang.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 350 DRAM May Fail Training on Cold Reset Description The DRAM DQS DLL may not lock after PWROK is asserted, resulting in a DRAM training failure. Potential Effect on System The system may fail to boot. Suggested Workaround During DRAM controller (DCT) initialization, system software should perform the following workaround to every enabled DCT in the system: 1.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 351 HyperTransport™ Technology LS2 Low-Power Mode May Not Function Correctly Description The HyperTransport™ technology LS2 low-power state may not function correctly in all systems. Potential Effect on System System hang or video distortion due to excessive latency. Suggested Workaround System software should program the Link Extended Control Registers[LS2En] (F0x[18C:170][8]) to 0b for all links.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 352 SYSCALL Instruction May Execute Incorrectly Due to Breakpoint Description A SYSCALL instruction executes incorrectly and an incorrect debug exception is taken when all of the following conditions are satisfied: • • • • • An enabled instruction breakpoint address matches the RIP of the SYSCALL instruction. The processor is in 64-bit mode or compatibility mode. The instruction would not generate any other exception.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 353 SYSRET Instruction May Execute Incorrectly Due to Breakpoint Description A SYSRET instruction executes incorrectly and an incorrect debug exception is taken when all of the following conditions are satisfied: • • • • • An enabled instruction breakpoint address matches the RIP of the SYSRET instruction. The processor is in 64-bit mode or compatibility mode. The instruction would not generate any other exception.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 354 HyperTransport™ Link Training Failure Description Some processors may fail HyperTransport™ link training at speeds greater than 2.0 GT/s. The link training failure may be intermittent. Potential Effect on System When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 355 DRAM Read Errors May Occur at Memory Speeds Higher than DDR2-800 Description The processor DRAM interface may miss a beat of data under conditions of back-to-back read bursts to the same chip select using DDR2-1066 memory speed, resulting in incorrect data read by the DRAM interface until a processor reset occurs. This issue is sensitive to processor VDDIO and VTT voltage settings.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 359 MEMCLK is Not Provided for Minimum Specified Time Before CKE Assertion Description During hardware DDR2 device initialization, the processor does not provide a running MEMCLK for the specified minimum time of 200 microseconds before CKE is asserted. Potential Effect on System No adverse effects have been observed.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 360 DRAM CKE and Address Drive Strength Values May Be Incorrect Description The processor does not correctly assign DRAM Output Driver Compensation Control Register[CkeDrvStren] (F2x[1,0]9C_x00[1:0]) and DRAM Output Driver Compensation Control Register[AddrCmdDrvStren] (F2x[1,0]9C_x00[9:8]) to the specified DRAM pins.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 361 Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost Description A #DB exception occurring in guest mode may be discarded under the following conditions: • • A trap-type #DB exception is generated in guest mode during execution of an instruction with an interrupt shadow, and The instruction that generated the exception is immediately followed by an instruction resulting in #VMEXIT.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 370 DRAM Read Errors May Occur at DDR2-800 Memory Speeds With Higher Read DQS Delays Description The processor DRAM interface may miss a beat of data under conditions of back-to-back read bursts to the same chip select using DDR2-800 memory speeds, resulting in incorrect data read by the DRAM interface until a processor reset occurs.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 372 Processor Read That Matches The Address of an Earlier Uncompleted Write May Be Incorrect Description Under highly specific and detailed internal timing conditions, processor data for a read may be corrupted when a read occurs that matches the address of an earlier uncompleted write or L3 eviction.
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41322 Rev. 3.84 Revision Guide for AMD Family 10h Processors August 2011 373 Processor Write to APIC Task Priority Register May Cause Error Status Bit to Set Description The processor may set Error Status Register[Send Accept Error] (APIC280[2]) after a write to a Task Priority Register (APIC080). This can occur only if a write to APIC080 follows a write to an Interrupt Command Register (APIC3[1, 0]0) that triggers an interprocessor interrupt (IPI).
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 374 Processor Read From L3 Cache May Return Stale Data Description Under highly specific and detailed internal timing conditions, a processor read from the L3 cache may return stale data. Potential Effect on System Unpredictable system behavior due to incorrect read data. Suggested Workaround System software should set F3x1B8[18] to 1b.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 378 Processor May Operate at Reduced Frequency Description When Product Information Register F3x1FC[31] is set, the reset values of the P-State Registers (MSRC001_00[68:64]) are not compliant with prior algorithms used to specify the P-state frequencies. Only one P-state register has bit 63 (PstateEn) set and the CPU frequency specified by this P-State register is below the maximum operating frequency for the processor.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 379 DDR3-1333 Configurations with Two DIMMs per Channel May Experience Unreliable Operation Description In systems with more than one DDR3-1333 unbuffered DIMM on a channel, the processor memory subsystem may exhibit unreliable operation over the allowable VDDIO voltage range. This erratum does not apply to DDR3-1333 configurations when only one DIMM per channel is populated.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 382 L3 Cache Index Disable Cannot Be Modified After L3 Cache is Enabled Description The processor does not support the disabling of L3 indices using the L3 Cache Index Disable Registers (F3x[1C0, 1BC]) after the cache subsystem has been enabled (CR0[CD] = 0b). Potential Effect on System If software modifies F3x[1C0, 1BC] after the L3 cache has been enabled using CR0[CD], unpredictable system behavior may result.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 383 CPU Core May Machine Check When System Software Changes Page Tables Dynamically Description If system software performs uncommon methods to change the page size of an active page table that is valid, the CPU core may, under a highly specific and detailed set of conditions, form duplicate TLB entries for a single linear address.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 384 DRAM Prefetch May Cause System Hang When Probe Filter is Enabled Description When the processor is accessing memory with the probe filter and DRAM prefetch enabled, a DRAM prefetch may not complete. Potential Effect on System System hang. Suggested Workaround System software should set the Memory Controller Configuration High[PrefIoDis, PrefCpuDis] (F2x11C[13:12] = 11b) if probe filter is enabled.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 385 Processor May Report Incorrect Address For an L3 Cache Error Machine Check Description The processor may report an incorrect address at NB Machine Check Address Register MSR0000_0412 when executing a machine check for an L3 cache error. In addition, when disabling an L3 cache index by writing to L3 Cache Index Disable Registers F3x[1C0, 1BC] [Index], the processor may not disable the intended L3 cache index.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 386 HyperTransport™ Link in Retry Mode That Receives Repeated Invalid Packets May Cause MCA Exception Description Under highly specific and detailed internal timing conditions, a HyperTransport™ link in retry mode that receives repeated invalid packets in a specific sequence may cause the processor to generate a link data buffer overflow MCA exception.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 387 Performance Counters Do Not Accurately Count L3 Cache Evictions Description The processor does not report the correct count of L3 cache evictions when Performance Event Select Register (PERF_CTL[3:0]) MSRC001_000[3:0][EventSelect] is 4E3h. This erratum applies to all unit mask settings for this event. Potential Effect on System Performance monitoring software will not be able to count L3 cache evictions with this event counter.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 388 L3 Cache Scrubbing Does Not Bypass Disabled L3 Cache Locations Description The processor does not discontinue scrubbing L3 cache locations that are disabled using the L3 Cache Index Disable Registers F3x[1C0, 1BC]. Potential Effect on System ECC errors that occur when scrubbing disabled L3 cache locations can generate unexpected machine check exceptions.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 389 HyperTransport™ Link in Retry Mode May Consume Link Packet Buffer Incorrectly Description Under highly specific and detailed internal timing conditions, a coherent HyperTransport™ link in retry mode that receives an invalid per-packet CRC may cause the processor to incorrectly consume a link packet buffer during link retry. This erratum applies only when F0x150[11:9] (HtRetryCrcDatIns) is set to a value other than 000b.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 391 HyperTransport™ Link RTT and RON Specification Violations Description The RTT and RON specifications of the HyperTransport™ link may be violated on some lanes. Potential Effect on System These violations do not result in any functional failures on HyperTransport™ links. Suggested Workaround None.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 393 Performance Monitor May Count Fastpath Double Operation Instructions Incorrectly Description The processor does not report the correct count for all fastpath double operation instructions when Performance Event Select Register (PERF_CTL[3:0]) MSRC001_000[3:0][EventSelect] is 0CCh. This erratum applies to all unit mask settings for this event.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 395 Incorrect Data Masking in Ganged DRAM Mode Description The DRAM controller may apply incorrect DRAM data masks when operating in ganged mode (DRAM Controller Select Low Register[DctGangEn] (F2x110[4]) is set to 1b). Potential Effect on System Unpredictable system behavior. Suggested Workaround The DRAM controllers should only be configured in the unganged mode.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 396 VLDT Maximum Current Specification Exceeded at HyperTransport™ Link Transfer Rates Up to 2.0 GT/s Description At HyperTransport™ link transfer rates up to 2.0 GT/s, VLDT maximum current (ILDT) may exceed the specified 500 mA per link limit. Potential Effect on System The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 397 VLDT Maximum Current Specification Exceeded on HyperTransport™ Links in Retry Mode Description HyperTransport™ links in retry mode may exceed the 1.4 A per link VLDT maximum current (ILDT) specification. Potential Effect on System The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 398 HyperTransport™ Links In Retry Mode May Experience High Bit Error Rate At Specific Link and Northbridge Clock Frequencies Description The processor HyperTransport™ link transmit FIFOs may underflow, resulting in bit errors. This erratum only applies when all of the following conditions are satisfied: • • • • Links are in retry mode. The HyperTransport link clock frequency is greater than the northbridge clock frequency.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 399 Memory Clear Initialization May Not Complete if DCT0 Fails Training Description During DRAM initialization, memory clearing that is initiated by writing 1b to DRAM Controller Select Low Register F2x110[3] (MemClrInit) may fail to complete when all of the following conditions are true: • • • All DRAM connected to DCT0 is disabled by system software as a result of a DRAM training failure.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 400 APIC Timer Interrupt Does Not Occur in Processor C-States Description An APIC timer interrupt that becomes pending in low-power states C1E or C3 will not cause the processor to enter the C0 state even if the interrupt is enabled by Timer Local Vector Table Entry[Mask], APIC320[16]). APIC timer functionality is otherwise unaffected.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 405 HyperTransport™ Link May Fail to Complete Training Description HyperTransport™ links may fail to re-train when resuming from LS2 low-power mode or following a warm reset. The failure may be package-specific and sensitive to longer HyperTransport links that contain multiple connectors. Potential Effect on System System hang.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 406 Processor Does Not Perform BmStsClrOnHltEn Function Description The processor does not perform a write operation to clear the BM_STS bit when Interrupt Pending and CMP-Halt Register[BmStsClrOnHltEn] (MSRC001_0055[29]) is set. Potential Effect on System The ACPI-defined register BM_STS bit may not be cleared before entry into C1E mode.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 407 System May Hang Due to Stalled Probe Data Transfer Description Under highly detailed and specific internal timing conditions, a processor that has one or more processor cores in a cache-flushed state following a C1E exit, and one or more cores executing in C0 state, may not complete a data transfer for a probe. Potential Effect on System System hang.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 408 Processor AltVID Exit May Cause System Hang Description Under highly detailed and specific internal timing conditions, the processor may hang during an exit from the AltVID state. Potential Effect on System System hang. Suggested Workaround System software should set Clock Power/Timing Control 0 Register[NbClkDiv] (F3xD4[30:28]) to 100b.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 414 Processor May Send Mode Register Set Commands to DDR3 DIMM Incorrectly Description The processor may send a Mode Register Set (MRS) command to a DDR3 DIMM without satisfying the auto-refresh row cycle time programmed at the DRAM Timing High Register F2x[1, 0]8C. In addition, the processor may send an MRS command to a DDR3 DIMM that has an active bank.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 415 HLT Instructions That Are Not Intercepted May Cause System Hang Description In guest mode when VMCB.V_INTR_MASK flag is 1b, the processor may not process host interrupts if a guest executes a HLT instruction that is not intercepted. Potential Effect on System System hang. Suggested Workaround Hypervisors should intercept HLT instructions by setting VMCB.Intercept_HLT (offset 00Ch bit 24) to 1b.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 416 DRAM Error Injection May Interfere With Power Management Events Description The value in the NB Array Address Register (F3xB8) may change during a stop-clock throttling event, C1E entry or C3 entry. In addition, a non-zero value in F3xB8 may cause a failure during stop-clock throttling or C1E or C3 mode entry. Potential Effect on System Unpredictable system behavior.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 417 Processor May Violate Tstab for Registered DDR3-1333 DIMMs Description Prior to asserting CKE during self-refresh exit, the processor may not provide a stable MEMCLK for the DIMM Tstab period of 6 microseconds. While MEMCLK is running for over 6 microseconds, one or more missing pulses may exist. The processor provides at least 4.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 418 Host Mapping of Physical Page Zero May Cause Incorrect Translation Description Under highly specific and detailed architectural conditions, the processor may use an incorrect cached copy of translation tables during a SVM nested page translation. This condition requires that the host be in legacy physical address extension (PAE) mode and that the guest address translation tables reside in physical page zero.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 419 C32r1 Package Processor May Report Incorrect PkgType Description A processor in a C32r1 package may report an incorrect PkgType of 0001b in CPUID Fn8000_0001_EBX[31:28]. This is the package type encoding for AM2r2/AM3 packages instead of the correct C32r1 package type encoding of 0101b. Potential Effect on System Software may incorrectly report the package type and incorrectly initialize package-specific features.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 420 Instruction-Based Sampling Engine May Generate Interrupt that Cannot Be Cleared Description A micro-op that is tagged by the Instruction-Based Sampling (IBS) execution engine shortly before the software clears the IBS Execution Control Register[IbsOpEn] (MSRC001_1033[17]) may create a condition in which the IBS sampling engine continuously generates an interrupt. This condition can exist even if IBS is not re-enabled.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 421 Performance Monitors for Fence Instructions May Increment Due to Floating-Point Instructions Description The processor may increment the count for LFENCE, SFENCE or MFENCE instructions (Performance Event Select Register (PERF_CTL[3:0]) MSRC001_000[3:0][EventSelect] is 1D3h, 1D4h or 1D5h respectively) when unrelated floating-point operations are executed.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 437 L3 Cache Performance Events May Not Reliably Track Processor Core Description The following L3 cache performance events may increment for events caused by cores that are not being tracked and may not increment for events caused by cores that are being tracked. • • • • • F4x1C8 L3 Hit Statistics Register. EventSelect 4E0h Read Request to L3 Cache when the unit mask is not Fxh.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 438 Access to MSRC001_0073 C-State Base Address Results in a #GP Fault Description An access to MSRC001_0073 C-State Base Address will result in a #GP fault. Potential Effect on System BIOS that attempts to enable an I/O C-state will generate an exception. Suggested Workaround Contact your AMD representative for information on a BIOS update.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 439 DQS Receiver Enable Training May Find Incorrect Delay Value Description Under highly specific and internal conditions, the algorithm for DQS Receiver Enable Training may incorrectly place the delay value for the DRAM DQS Receiver Enable Timing Control Register F2x[1,0]9C_x[2B:10] before the read preamble.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 440 SMM Save State Host CR3 Value May Be Incorrect Description The processor writes bits 47:32 as 0000h of SMM Save State offset FF38h (Host CR3) when all of the following conditions are met: • • • • • An SMI occurs while in a guest context. SMIs are not intercepted to the hypervisor and cause a direct transition from the guest to the SMM code. Nested paging is in use (VMCB offset 090h[0], NP_ENABLE, is 1b).
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 441 Move from Stack Pointer to Debug or Control Register May Result in Incorrect Value Description A move from the stack pointer to a debug register or a control register may store a value that does not include one or more updates based on completed pushes, pops, near calls or returns. This erratum does not occur if the instruction encoding uses the standard encoding of ModRM[7:6]=11b to indicate a register-to-register move.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 443 Instruction-Based Sampling May Not Indicate Store Operation Description Instruction-Based Sampling (IBS) tagging on certain micro-ops that perform both the load and store operation may only set the IBS Op Data 3 Register[IbsLdOp] (MSRC001_1037[0]) and not IBS Op Data 3 Register[IbsStOp] (MSRC001_1037[1]). Potential Effect on System Inaccuracies in performance monitoring software may be experienced. Suggested Workaround None.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 459 DDR3-1333 Configurations with Three DIMMs per Channel May Experience Unreliable Operation Description In systems with three DDR3-1333 registered DIMMs on a channel, the processor memory subsystem may exhibit unreliable operation over the allowable voltage ranges. Potential Effect on System Memory system failure, leading to DRAM ECC machine check errors.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 486 Processor Thermal Data Sheet Specification Error Description The AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet, order #43374 for G34r1 and C32r1 OPNs incorrectly documented an “IDD Max” value that was based on current at “Thermal Design Power” (TDP). The maximum current for these processors would be properly defined at “MaxPower” and documented as the “Thermal Design Current” (TDC).
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 521 C1E Resume Failure With Certain Registered DIMM Configurations Description Processors may fail to exit self-refresh mode under the following conditions: • • • • LDTSTOP# is asserted less than 20 uS after it was last deasserted. The system configuration includes a processor node having dual or quad rank DDR3 Registered DIMMs on one channel and only single rank or no DIMMs on the other channel.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 550 Latency Performance Counters Are Not Accurate Description Latency performance counters MSRC001_000[3:0][7:0] (EventSelect) in the range 1E2h to 1E7h are not accurate when L3 speculative miss prefetching is enabled (F2x1B0[13] = 0b, Extended Memory Controller Configuration Low[SpecPrefDis]). Potential Effect on System Performance monitoring software cannot accurately measure latency events.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 610 Processor with Message-Triggered C1E Enabled May Report a False L3 LRU or Tag Machine Check Description During an exit from message-triggered C1E state (LDTSTOP# deassertion) that is less than 10 microseconds after the STOPGRANT message, the processor may report a false uncorrectable machine check exception for either an L3 LRU or tag error.
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 625 SB-RMI Writes May Not Be Observed by Processor Description After a write using the APML SB-RMI interface to either the Inbound Message Registers (SBRMI_x3[F:8]) or Software Interrupt Register (SBRMI_x40), the processor may observe the previous contents (as if the write did not occur) when reading these same registers using the SBI Address/Data registers (F3x1E8 and F3x1EC).
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.84 August 2011 643 Processor May Increment CPU Watchdog Timer at an Incorrect Rate Description The rate at which the CPU watchdog timer counter increments may be significantly higher than the rate specified in the CPU Watchdog Timer Register[CpuWdtCountSel, CpuWdtCountBase] (MSRC001_0074[6:3 and 2:1]).
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41322 Rev. 3.84 August 2011 Revision Guide for AMD Family 10h Processors 669 Local Vector Table Interrupt May Cause C1E Entry Without Caches Flushed Description An interrupt assigned to the APIC local vector table (LVT) that becomes pending in a short interval around entry to C1E mode may cause the processor to incorrectly enter C1E mode after storing the interrupt vector but before executing the first instruction of the interrupt handler.
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