user manual

AMD Athlon™ Processor Microarchitecture 135
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Integer Scheduler
The integer scheduler is based on a three-wide queuing system
(also known as a reservation station) that feeds three integer
execution positions or pipes. The reservation stations are six
entries deep, for a total queuing system of 18 integer
MacroOPs.Each reservation station divides the MacroOPs into
integer and address generation OPs, as required.
Integer Execution Unit
The integer execution pipeline consists of three identical
pipes—0, 1, and 2. Each integer pipe consists of an integer
execution unit (IEU) and an address generation unit (AGU).
The integer execution pipeline is organized to match the three
MacroOP dispatch pipes in the ICU as shown in Figure 2 on
page 135. MacroOPs are broken down into OPs in the
schedulers. OPs issue when their operands are available either
from the register file or result buses.
OPs are executed when their operands are available. OPs from
a single MacroOP can execute out-of-order. In addition, a
particular integer pipe can be executing two OPs from different
MacroOPs (one in the IEU and one in the AGU) at the same
time.
Figure 2. Integer Execution Pipeline
IEU 1
IEU 1
Instruction Control Unit and Register Files
Integer M ultiply (IM UL)
Integer M ultiply (IM UL)
IEU 0
IEU 0
AGU0
AGU0
AGU1
AGU1
IEU 2
IEU 2
AGU2
AGU2
MacroOPs
MacroOPs
Pipeline
Pipeline
Stage
Stage
Integer Scheduler
(18-entry)
7
7
8
8