user manual

136 AMD Athlon™ Processor Microarchitecture
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Each of the three IEUs are general purpose in that each
performs logic functions, arithmetic functions, conditional
functions, divide step functions, status flag multiplexing, and
branch resolutions. The AGUs calculate the logical addresses
for loads, stores, and LEAs. A load and store unit reads and
writes data to and from the L1 data cache. The integer
scheduler sends a completion status to the ICU when the
outstanding OPs for a given MacroOP are executed.
All integer operations can be handled within any of the three
IEUs with the exception of multiplies. Multiplies are handled
by a pipelined multiplier that is attached to the pipeline at pipe
0. See Figure 2 on page 135. Multiplies always issue to integer
pipe 0, and the issue logic creates results bus bubbles for the
multiplier in integer pipes 0 and 1 by preventing non-multiply
OPs from issuing at the appropriate time.
Floating-Point Scheduler
The AMD Athlon processor floating-point logic is a
high-performance, fully-pipelined, superscalar, out-of-order
execution unit. It is capable of accepting three MacroOPs of any
mixture of x87 floating-point, 3DNow! or MMX operations per
cycle.
The floating-point scheduler handles register renaming and has
a dedicated 36-entry scheduler buffer organized as 12 lines of
three MacroOPs each. It also performs OP issue, and
out-of-order execution. The floating-point scheduler
communicates with the ICU to retire a MacroOP, to manage
comparison results from the FCOMI instruction, and to back
out results from a branch misprediction.