user manual

AMD Athlon™ Processor Microarchitecture 137
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Floating-Point Execution Unit
The floating-point execution unit (FPU) is implemented as a
coprocessor that has its own out-of-order control in addition to
the data path. The FPU handles all register operations for x87
instructions, all 3DNow! operations, and all MMX operations.
The FPU consists of a stack renaming unit, a register renaming
unit, a scheduler, a register file, and three parallel execution
units. Figure 3 shows a block diagram of the dataflow through
the FPU.
Figure 3. Floating-Point Unit Block Diagram
As shown in Figure 3 on page 137, the floating-point logic uses
three separate execution positions or pipes for superscalar x87,
3DNow! and MMX operations. The first of the three pipes is
generally known as the adder pipe (FADD), and it contains
3DNow! add, MMX ALU/shifter, and floating-point add
execution units. The second pipe is known as the multiplier
(FMUL). It contains a 3DNow!/MMX multiplier/reciprocal unit,
an MMX ALU and a floating-point multiplier/divider/square
root unit. The third pipe is known as the floating-point
load/store (FSTORE), which handles floating-point constant
loads (FLDZ, FLDPI, etc.), stores, FILDs, as well as many OP
primitives used in VectorPath sequences.
Instruction Control Unit
Instruction Control Unit
FADD
• MMX™ ALU
• 3DNow!™
FADD
• MMX™ ALU
• 3DNow!™
FSTORE
FSTORE
FMUL
• MMX ALU
• MMX Mul
• 3DNow!
FMUL
• MMX ALU
• MMX Mul
• 3DNow!
Stack Map
Stack Map
Register Rename
Register Rename
Scheduler (36-entry)
Scheduler (36-entry)
FPU Register File (88-entry)
FPU Register File (88-entry)
Pipeline
Pipeline
Stage
Stage
7
7
8
8
11
11
9
9
10
10
12
12
to
to
15
15