user manual

146 Floating-Point Pipeline Stages
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Floating-Point Pipeline Stages
The floating-point unit (FPU) is implemented as a coprocessor
that has its own out-of-order control in addition to the data
path. The FPU handles all register operations for x87
instructions, all 3DNow! operations, and all MMX operations.
The FPU consists of a stack renaming unit, a register renaming
unit, a scheduler, a register file, and three parallel execution
units. Figure 9 shows a block diagram of the dataflow through
the FPU.
Figure 9. Floating-Point Unit Block Diagram
The floating-point pipeline stages 7–15 are shown in Figure 10
and described in the following sections. Note that the
floating-point pipe and integer pipe separates at cycle 7.
Figure 10. Floating-Point Pipeline Stages
Instruction Control Unit
Instruction Control Unit
FADD
• MMX™ ALU
• 3DNow!™
FADD
• MMX™ ALU
• 3DNow!™
FSTORE
FSTORE
FMUL
• MMX ALU
• MMX Mul
• 3DNow!
FMUL
• MMX ALU
• MMX Mul
• 3DNow!
Stack Map
Stack Map
Register Rename
Register Rename
Scheduler (36-entry)
Scheduler (36-entry)
FPU Register File (88-entry)
FPU Register File (88-entry)
Pipeline
Pipeline
Stage
Stage
7
7
8
8
11
11
9
9
10
10
12
12
to
to
15
15
STKREN REGREN SCHEDW SCHED FREG
7
8
9
10
11
FEXE1
12
FEXE4
15