user manual

164 Performance Counter Usage
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
greater than or equal to the counter mask. Otherwise if this
field is zero, then the counter increments by the total number of
events.
Table 11. Performance-Monitoring Counters
Event
Number
Source
Unit
Notes / Unit Mask (bits 15–8) Event Description
20h LS
1xxx_xxxxb = reserved
x1xx_xxxxb = HS
xx1x_xxxxb = GS
xxx1_xxxxb = FS
xxxx_1xxxb = DS
xxxx_x1xxb = SS
xxxx_xx1xb = CS
xxxx_xxx1b = ES
Segment register loads
21h LS Stores to active instruction stream
40h DC Data cache accesses
41h DC Data cache misses
42h DC
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
Data cache refills
43h DC
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
Data cache refills from system
44h DC
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
Data cache writebacks
45h DC L1 DTLB misses and L2 DTLB hits
46h DC L1 and L2 DTLB misses
47h DC Misaligned data references
64h BU DRAM system requests