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Performance Counter Usage 165
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
65h BU
1xxx_xxxxb = reserved
x1xx_xxxxb = WB
xx1x_xxxxb = WP
xxx1_xxxxb = WT
bits 11–10 = reserved
xxxx_xx1xb = WC
xxxx_xxx1b = UC
System requests with the selected type
73h BU
bits 15–11 = reserved
xxxx_x1xxb = L2 (L2 hit and no DC
hit)
xxxx_xx1xb = Data cache
xxxx_xxx1b = Instruction cache
Snoop hits
74h BU
bits 15–10 = reserved
xxxx_xx1xb = L2 single bit error
xxxx_xxx1b = System single bit error
Single-bit ECC errors detected/corrected
75h BU
bits 15–12 = reserved
xxxx_1xxxb = I invalidates D
xxxx_x1xxb = I invalidates I
xxxx_xx1xb = D invalidates D
xxxx_xxx1b = D invalidates I
Internal cache line invalidates
76h BU
Cycles processor is running (not in HLT
or STPCLK)
79h BU
1xxx_xxxxb = Data block write from
the L2 (TLB RMW)
x1xx_xxxxb = Data block write from
the DC
xx1x_xxxxb = Data block write from
the system
xxx1_xxxxb = Data block read data
store
xxxx_1xxxb = Data block read data
load
xxxx_x1xxb = Data block read
instruction
xxxx_xx1xb = Tag write
xxxx_xxx1b = Tag read
L2 requests
Table 11. Performance-Monitoring Counters (Continued)
Event
Number
Source
Unit
Notes / Unit Mask (bits 15–8) Event Description