user manual

166 Performance Counter Usage
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
7Ah BU
Cycles that at least one fill request
waited to use the L2
80h PC Instruction cache fetches
81h PC Instruction cache misses
82h PC Instruction cache refills from L2
83h PC Instruction cache refills from system
84h PC L1 ITLB misses (and L2 ITLB hits)
85h PC (L1 and) L2 ITLB misses
86h PC Snoop resyncs
87h PC Instruction fetch stall cycles
88h PC Return stack hits
89h PC Return stack overflow
C0h FR
Retired instructions (includes
exceptions, interrupts, resyncs)
C1h FR Retired Ops
C2h FR
Retired branches (conditional,
unconditional, exceptions, interrupts)
C3h FR Retired branches mispredicted
C4h FR Retired taken branches
C5h FR Retired taken branches mispredicted
C6h FR Retired far control transfers
C8h FR Retired near returns
C9h FR Retired near returns mispredicted
CAh FR
Retired indirect branches with target
mispredicted
CDh FR Interrupts masked cycles (IF=0)
CEh FR
Interrupts masked while pending cycles
(INTR while IF=0)
CFh FR Number of taken hardware interrupts
D0h FR Instruction decoder empty
D1h FR
Dispatch stalls (event masks D2h
through DAh below combined)
D2h FR Branch abort to retire
D3h FR Serialize
D4h FR Segment load stall
Table 11. Performance-Monitoring Counters (Continued)
Event
Number
Source
Unit
Notes / Unit Mask (bits 15–8) Event Description