user manual

22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Introduction 171
Appendix E
Programming the MTRR and
PAT
Introduction
The AMD Athlon™ processor includes a set of memory type
and range registers (MTRRs) to control cacheability and access
to specified memory regions. The processor also includes the
Page Address Table for defining attributes of pages. This
chapter documents the use and capabilities of this feature.
The purpose of the MTRRs is to provide system software with
the ability to manage the memory mapping of the hardware.
Both the BIOS software and operating systems utilize this
capability. The AMD Athlon processor’s implementation is
compatible to the Pentium
®
II. Prior to the MTRR mechanism,
chipsets usually provided this capability.
Memory Type Range Register (MTRR) Mechanism
The memory type and range registers allow the processor to
determine cacheability of various memory locations prior to
bus access and to optimize access to the memory system. The
AMD Athlon processor implements the MTRR programming
model in a manner compatible with Pentium II.