user manual

178 Page Attribute Table (PAT)
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Accessing the PAT A 3-bit index consisting of the PATi, PCD, and PWT bits of the
page table entry, is used to select one of the seven PAT register
fields to acquire the memory type for the desired page (PATi is
defined as bit 7 for 4-Kbyte PTEs and bit 12 for PDEs which
map to 2-Mbyte or 4-Mbyte pages). The memory type from the
PAT is used instead of the PCD and PWT for the effective
memory type.
A 2-bit index consisting of PCD and PWT bits of the page table
entry, is used to select one of four PAT register fields when PAE
(page address extensions) is enabled, or when the PDE doesn’t
describe a large page. In the latter case, the PATi bit for a PTE
(bit 7) corresponds to the page size bit in a PDE. Therefore, the
OS should only use PA0-3 when setting the memory type for a
page table that is also used as a page directory. See Table 14 on
page 178.
MTRRs and PAT The processor contains MTRRs as described earlier which
provide a limited way of assigning memory types to specific
regions. However, the page tables allow memory types to be
assigned to the pages used for linear to physical translation.
The memory type as defined by PAT and MTRRs are combined
to determine the effective memory type as listed in Table 15
and Table 16. Shaded areas indicated reserved settings.
Table 14. PATi 3-Bit Encodings
PATi PCD PWT PAT Entry Reset Value
00 0 0
00 1 1
01 0 2
01 1 3
10 0 4
10 1 5
11 0 6
11 1 7