user manual

188 Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
■ disp16/32—16-bit or 32-bit displacement value
■ disp32/48—32-bit or 48-bit displacement value
■ eXX—register width depending on the operand size
■ mem32real—32-bit floating-point value in memory
■ mem64real—64-bit floating-point value in memory
■ mem80real—80-bit floating-point value in memory
■ mmreg—MMX/3DNow! register
■ mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
■ mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
The second and third columns list all applicable encoding
opcode bytes.
The fourth column lists the modR/M byte used by the
instruction. The modR/M byte defines the instruction as
register or memory form. If mod bits 7 and 6 are documented as
mm (memory form), mm can only be 10b, 01b, or 00b.
The fifth column lists the type of instruction decode—
DirectPath or VectorPath (see “DirectPath Decoder” on page
133 and “VectorPath Decoder” on page 133 for more
information). The AMD Athlon™ processor enhanced decode
logic can process three instructions per clock.
The FPU, MMX, and 3DNow! instruction tables have an
additional column that lists the possible FPU execution
pipelines available for use by any particular DirectPath
decoded operation. Typically, VectorPath instructions require
more than one execution pipe resource.
Table 19. Integer Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
AAA 37h VectorPath
AAD D5h 0Ah VectorPath
AAM D4h 0Ah VectorPath
AAS 3Fh VectorPath