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Instruction Dispatch and Execution Resources 211
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
PUNPCKHDQ mmreg1, mmreg2 0Fh 6Ah 11-xxx-xxx DirectPath FADD/FMUL
PUNPCKHDQ mmreg, mem64 0Fh 6Ah mm-xxx-xxx DirectPath FADD/FMUL
PUNPCKHWD mmreg1, mmreg2 0Fh 69h 11-xxx-xxx DirectPath FADD/FMUL
PUNPCKHWD mmreg, mem64 0Fh 69h mm-xxx-xxx DirectPath FADD/FMUL
PUNPCKLBW mmreg1, mmreg2 0Fh 60h 11-xxx-xxx DirectPath FADD/FMUL
PUNPCKLBW mmreg, mem64 0Fh 60h mm-xxx-xxx DirectPath FADD/FMUL
PUNPCKLDQ mmreg1, mmreg2 0Fh 62h 11-xxx-xxx DirectPath FADD/FMUL
PUNPCKLDQ mmreg, mem64 0Fh 62h mm-xxx-xxx DirectPath FADD/FMUL
PUNPCKLWD mmreg1, mmreg2 0Fh 61h 11-xxx-xxx DirectPath FADD/FMUL
PUNPCKLWD mmreg, mem64 0Fh 61h mm-xxx-xxx DirectPath FADD/FMUL
PXOR mmreg1, mmreg2 0Fh EFh 11-xxx-xxx DirectPath FADD/FMUL
PXOR mmreg, mem64 0Fh EFh mm-xxx-xxx DirectPath FADD/FMUL
Table 21. MMX™ Extensions
Instruction Mnemonic
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Notes
MASKMOVQ mmreg1, mmreg2 0Fh F7h VectorPath FADD/FMUL/FSTORE
MOVNTQ mem64, mmreg 0Fh E7h DirectPath FSTORE
PAVGB mmreg1, mmreg2 0Fh E0h 11-xxx-xxx DirectPath FADD/FMUL
PAVGB mmreg, mem64 0Fh E0h mm-xxx-xxx DirectPath FADD/FMUL
PAVGW mmreg1, mmreg2 0Fh E3h 11-xxx-xxx DirectPath FADD/FMUL
PAVGW mmreg, mem64 0Fh E3h mm-xxx-xxx DirectPath FADD/FMUL
PEXTRW reg32, mmreg, imm8 0Fh C5h VectorPath
PINSRW mmreg, reg32, imm8 0Fh C4h VectorPath
PINSRW mmreg, mem16, imm8 0Fh C4h VectorPath
PMAXSW mmreg1, mmreg2 0Fh EEh 11-xxx-xxx DirectPath FADD/FMUL
PMAXSW mmreg, mem64 0Fh EEh mm-xxx-xxx DirectPath FADD/FMUL
PMAXUB mmreg1, mmreg2 0Fh DEh 11-xxx-xxx DirectPath FADD/FMUL
PMAXUB mmreg, mem64 0Fh DEh mm-xxx-xxx DirectPath FADD/FMUL
PMINSW mmreg1, mmreg2 0Fh EAh 11-xxx-xxx DirectPath FADD/FMUL
Notes:
1. For the PREFETCHNTA/T0/T1/T2 instructions, the mem8 value refers to an address in the 64-byte line that will be prefetched.
Table 20. MMX™ Instructions (Continued)
Instruction Mnemonic
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
FPU Pipe(s) Notes
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.