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Instruction Dispatch and Execution Resources 217
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Table 23. 3DNow!™ Instructions
Instruction Mnemonic
Prefix
Byte(s)
imm8
ModR/M
Byte
Decode
Type
FPU
Pipe(s)
Note
FEMMS 0Fh 0Eh DirectPath FADD/FMUL/FSTORE 2
PAVGUSB mmreg1, mmreg2 0Fh, 0Fh BFh 11-xxx-xxx DirectPath FADD/FMUL
PAVGUSB mmreg, mem64 0Fh, 0Fh BFh mm-xxx-xxx DirectPath FADD/FMUL
PF2ID mmreg1, mmreg2 0Fh, 0Fh 1Dh 11-xxx-xxx DirectPath FADD
PF2ID mmreg, mem64 0Fh, 0Fh 1Dh mm-xxx-xxx DirectPath FADD
PFACC mmreg1, mmreg2 0Fh, 0Fh AEh 11-xxx-xxx DirectPath FADD
PFACC mmreg, mem64 0Fh, 0Fh AEh mm-xxx-xxx DirectPath FADD
PFADD mmreg1, mmreg2 0Fh, 0Fh 9Eh 11-xxx-xxx DirectPath FADD
PFADD mmreg, mem64 0Fh, 0Fh 9Eh mm-xxx-xxx DirectPath FADD
PFCMPEQ mmreg1, mmreg2 0Fh, 0Fh B0h 11-xxx-xxx DirectPath FADD
PFCMPEQ mmreg, mem64 0Fh, 0Fh B0h mm-xxx-xxx DirectPath FADD
PFCMPGE mmreg1, mmreg2 0Fh, 0Fh 90h 11-xxx-xxx DirectPath FADD
PFCMPGE mmreg, mem64 0Fh, 0Fh 90h mm-xxx-xxx DirectPath FADD
PFCMPGT mmreg1, mmreg2 0Fh, 0Fh A0h 11-xxx-xxx DirectPath FADD
PFCMPGT mmreg, mem64 0Fh, 0Fh A0h mm-xxx-xxx DirectPath FADD
PFMAX mmreg1, mmreg2 0Fh, 0Fh A4h 11-xxx-xxx DirectPath FADD
PFMAX mmreg, mem64 0Fh, 0Fh A4h mm-xxx-xxx DirectPath FADD
PFMIN mmreg1, mmreg2 0Fh, 0Fh 94h 11-xxx-xxx DirectPath FADD
PFMIN mmreg, mem64 0Fh, 0Fh 94h mm-xxx-xxx DirectPath FADD
PFMUL mmreg1, mmreg2 0Fh, 0Fh B4h 11-xxx-xxx DirectPath FMUL
PFMUL mmreg, mem64 0Fh, 0Fh B4h mm-xxx-xxx DirectPath FMUL
PFRCP mmreg1, mmreg2 0Fh, 0Fh 96h 11-xxx-xxx DirectPath FMUL
PFRCP mmreg, mem64 0Fh, 0Fh 96h mm-xxx-xxx DirectPath FMUL
PFRCPIT1 mmreg1, mmreg2 0Fh, 0Fh A6h 11-xxx-xxx DirectPath FMUL
PFRCPIT1 mmreg, mem64 0Fh, 0Fh A6h mm-xxx-xxx DirectPath FMUL
PFRCPIT2 mmreg1, mmreg2 0Fh, 0Fh B6h 11-xxx-xxx DirectPath FMUL
PFRCPIT2 mmreg, mem64 0Fh, 0Fh B6h mm-xxx-xxx DirectPath FMUL
PFRSQIT1 mmreg1, mmreg2 0Fh, 0Fh A7h 11-xxx-xxx DirectPath FMUL
PFRSQIT1 mmreg, mem64 0Fh, 0Fh A7h mm-xxx-xxx DirectPath FMUL
PFRSQRT mmreg1, mmreg2 0Fh, 0Fh 97h 11-xxx-xxx DirectPath FMUL
Notes:
1. For the PREFETCH and PREFETCHW instructions, the mem8 value refers to an address in the 64-byte line that will be
prefetched.
2. The byte listed in the column titled ‘imm8’ is actually the opcode byte.