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DirectPath Instructions 223
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
MOV mem16/32, imm16/32
MOVSX reg16/32, mreg8
MOVSX reg16/32, mem8
MOVSX reg32, mreg16
MOVSX reg32, mem16
MOVZX reg16/32, mreg8
MOVZX reg16/32, mem8
MOVZX reg32, mreg16
MOVZX reg32, mem16
NEG mreg8
NEG mem8
NEG mreg16/32
NEG mem16/32
NOP (XCHG EAX, EAX)
NOT mreg8
NOT mem8
NOT mreg16/32
NOT mem16/32
OR mreg8, reg8
OR mem8, reg8
OR mreg16/32, reg16/32
OR mem16/32, reg16/32
OR reg8, mreg8
OR reg8, mem8
OR reg16/32, mreg16/32
OR reg16/32, mem16/32
OR AL, imm8
OR EAX, imm16/32
OR mreg8, imm8
OR mem8, imm8
OR mreg16/32, imm16/32
OR mem16/32, imm16/32
OR mreg16/32, imm8 (sign extended)
OR mem16/32, imm8 (sign extended)
Table 25. DirectPath Integer Instructions (Continued)
Instruction Mnemonic
PUSH EAX
PUSH ECX
PUSH EDX
PUSH EBX
PUSH ESP
PUSH EBP
PUSH ESI
PUSH EDI
PUSH imm8
PUSH imm16/32
RCL mreg8, imm8
RCL mreg16/32, imm8
RCL mreg8, 1
RCL mem8, 1
RCL mreg16/32, 1
RCL mem16/32, 1
RCL mreg8, CL
RCL mreg16/32, CL
RCR mreg8, imm8
RCR mreg16/32, imm8
RCR mreg8, 1
RCR mem8, 1
RCR mreg16/32, 1
RCR mem16/32, 1
RCR mreg8, CL
RCR mreg16/32, CL
ROL mreg8, imm8
ROL mem8, imm8
ROL mreg16/32, imm8
ROL mem16/32, imm8
ROL mreg8, 1
ROL mem8, 1
ROL mreg16/32, 1
ROL mem16/32, 1
Table 25. DirectPath Integer Instructions (Continued)
Instruction Mnemonic