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DirectPath Instructions 225
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
SETL/SETNGE mreg8
SETL/SETNGE mem8
SETGE/SETNL mreg8
SETGE/SETNL mem8
SETLE/SETNG mreg8
SETLE/SETNG mem8
SETG/SETNLE mreg8
SETG/SETNLE mem8
SHL/SAL mreg8, imm8
SHL/SAL mem8, imm8
SHL/SAL mreg16/32, imm8
SHL/SAL mem16/32, imm8
SHL/SAL mreg8, 1
SHL/SAL mem8, 1
SHL/SAL mreg16/32, 1
SHL/SAL mem16/32, 1
SHL/SAL mreg8, CL
SHL/SAL mem8, CL
SHL/SAL mreg16/32, CL
SHL/SAL mem16/32, CL
SHR mreg8, imm8
SHR mem8, imm8
SHR mreg16/32, imm8
SHR mem16/32, imm8
SHR mreg8, 1
SHR mem8, 1
SHR mreg16/32, 1
SHR mem16/32, 1
SHR mreg8, CL
SHR mem8, CL
SHR mreg16/32, CL
SHR mem16/32, CL
STC
SUB mreg8, reg8
Table 25. DirectPath Integer Instructions (Continued)
Instruction Mnemonic
SUB mem8, reg8
SUB mreg16/32, reg16/32
SUB mem16/32, reg16/32
SUB reg8, mreg8
SUB reg8, mem8
SUB reg16/32, mreg16/32
SUB reg16/32, mem16/32
SUB AL, imm8
SUB EAX, imm16/32
SUB mreg8, imm8
SUB mem8, imm8
SUB mreg16/32, imm16/32
SUB mem16/32, imm16/32
SUB mreg16/32, imm8 (sign extended)
SUB mem16/32, imm8 (sign extended)
TEST mreg8, reg8
TEST mem8, reg8
TEST mreg16/32, reg16/32
TEST mem16/32, reg16/32
TEST AL, imm8
TEST EAX, imm16/32
TEST mreg8, imm8
TEST mem8, imm8
TEST mreg8, imm16/32
TEST mem8, imm16/32
WAIT
XCHG EAX, EAX
XOR mreg8, reg8
XOR mem8, reg8
XOR mreg16/32, reg16/32
XOR mem16/32, reg16/32
XOR reg8, mreg8
XOR reg8, mem8
XOR reg16/32, mreg16/32
Table 25. DirectPath Integer Instructions (Continued)
Instruction Mnemonic