user manual

228 DirectPath Instructions
AMD Athlon Processor x86 Code Optimization
22007E/0November 1999
PSRLD mmreg, imm8
PSRLQ mmreg1, mmreg2
PSRLQ mmreg, mem64
PSRLQ mmreg, imm8
PSRLW mmreg1, mmreg2
PSRLW mmreg, mem64
PSRLW mmreg, imm8
PSUBB mmreg1, mmreg2
PSUBB mmreg, mem64
PSUBD mmreg1, mmreg2
PSUBD mmreg, mem64
PSUBSB mmreg1, mmreg2
PSUBSB mmreg, mem64
PSUBSW mmreg1, mmreg2
PSUBSW mmreg, mem64
PSUBUSB mmreg1, mmreg2
PSUBUSB mmreg, mem64
PSUBUSW mmreg1, mmreg2
PSUBUSW mmreg, mem64
PSUBW mmreg1, mmreg2
PSUBW mmreg, mem64
PUNPCKHBW mmreg1, mmreg2
PUNPCKHBW mmreg, mem64
PUNPCKHDQ mmreg1, mmreg2
PUNPCKHDQ mmreg, mem64
PUNPCKHWD mmreg1, mmreg2
PUNPCKHWD mmreg, mem64
PUNPCKLBW mmreg1, mmreg2
PUNPCKLBW mmreg, mem64
PUNPCKLDQ mmreg1, mmreg2
PUNPCKLDQ mmreg, mem64
PUNPCKLWD mmreg1, mmreg2
PUNPCKLWD mmreg, mem64
PXOR mmreg1, mmreg2
Table 26. DirectPath MMX Instructions (Continued)
Instruction Mnemonic
PXOR mmreg, mem64
Table 27. DirectPath MMX Extensions
Instruction Mnemonic
MOVNTQ mem64, mmreg
PAVGB mmreg1, mmreg2
PAVGB mmreg, mem64
PAVGW mmreg1, mmreg2
PAVGW mmreg, mem64
PMAXSW mmreg1, mmreg2
PMAXSW mmreg, mem64
PMAXUB mmreg1, mmreg2
PMAXUB mmreg, mem64
PMINSW mmreg1, mmreg2
PMINSW mmreg, mem64
PMINUB mmreg1, mmreg2
PMINUB mmreg, mem64
PMULHUW mmreg1, mmreg2
PMULHUW mmreg, mem64
PSADBW mmreg1, mmreg2
PSADBW mmreg, mem64
PSHUFW mmreg1, mmreg2, imm8
PSHUFW mmreg, mem64, imm8
PREFETCHNTA mem8
PREFETCHT0 mem8
PREFETCHT1 mem8
PREFETCHT2 mem8
Table 26. DirectPath MMX Instructions (Continued)
Instruction Mnemonic