Specifications


SLAS495A− JUNE 2006 − REVISED OCTOBER 2007
www.ti.com
28
Delta-Sigma DAC
The audio digital-to-analog converter incorporates a third order multi-bit delta-sigma modulator followed by an
analog reconstruction filter. The DAC provides high-resolution, low−noise performance, using oversampling
and noise shaping techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter
followed by a continuous time RC filter. The analog FIR operates at 6.144 MHz (128x48 kHz, for Fsref of 48
kHz) or at 5.6448 MHz (128x44.1 kHz, for Fsref of 44.1 kHz). The DAC analog performance may be degraded
by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a
minimum (less than 50 ps).
DAC Digital Volume Control
The DAC has a digital volume control block, which implements programmable gain. The volume level can be
varied from 0 dB to –63.5 dB in 0.5 dB steps, in addition to a mute bit, independently for each channel. The
volume level of both channels can also be changed simultaneously by the master volume control. The gain is
implemented with a soft−stepping algorithm, which only changes the actual volume by one step per input
sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one
step per two input samples through D1 of control register 04H/Page 2.
Because of soft-stepping, the host does not know when the DAC has been completely muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. In order to help with this situation, the part provides a flag back to the host via a read-only register bit
(D2−D3 of control register 04H/page 2) that alerts the host when the part has completed the soft-stepping, and
the actual volume has reached the desired volume level. The soft-stepping feature can be disabled by
programming D14=1 in register 1DH in Page 2. If soft-stepping is enabled, the MCLK signal should be kept
applied to the device, until the DAC power-down flag is set. When this flag is set, the internal soft-stepping
process and power down sequence is complete, and the MCLK can be stopped if desired.
The TSC2111 also includes functionality to detect when the user switches on or off the de-emphasis or digital
audio processing functions, then (1) soft-mute the DAC volume control, (2) change the operation of the digital
effects processing and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The
circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired volume
level. At power-down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.