User guide

SENSORRAIL IIIE 8200-0593-03, REV. A
SERVICE GUIDE
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ATMEGA 128 Microcontroller
Note: The following information refers to diagrams
on pages 8 through 10.
The CPU is an ATMEGA 128, a low-power CMOS,
8-bit micro (µP) controller based on AVR enhanced
RISC architecture.
• The ATMEGA 128 combines a rich instruction
set with 32 general-purpose working registers.
• By executing powerful instructions in a single
clock cycle, the ATMEGA 128 achieves
throughputs approaching 1MIPS per MHz.
• Matrix switcher commands are received through
Port E (PE0, PE1) of the ATMEGA 128. Then,
IRIS or FOCUS codes extracted from the data
frame activate PWM drivers through
- Port B (PWM = motor speed),
- Port C (Cmd = CW or CCW rotation),
(Disable = motor ON or OFF), and (Brake).
• All remaining data from the frame are sent
directly to the dome camera through Port D
(PD2, PD3) using an RS-232 / RS-422 full
duplex converter.
• All the 32 registers connect to the Arithmetic
Logic Unit (ALU), enabling access to two
independent registers in one single instruction
executed in one clock cycle. The resulting
architecture is more code efficient while
achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATMEGA 128 µP has the following features:
• 128K bytes of in-system programmable flash
with read-while-write capabilities
• 4Kb EEPROM
• 4Kb SRAM
• 53 general-purpose I/O lines
• 32 general-purpose working registers
• Real-time counter (RTC)
• 4 flexible timer/counters with compare mode
and PWM
• 2 UARTs
• Byte oriented two-wire serial interface
• 8 channel, 10-bit ADC with an optional
differential input stage having programmable
gain
• Programmable watchdog timer with internal
oscillator
• SPI serial port
• IEEE 1149.1 STD. compliant JTAG test
interface (also used for accessing the on-chip
debug system and programming)
• 6 software-selectable power saving modes
• On-chip ISP flash enables program memory to
be reprogrammed in-system through an SPI
serial interface, conventional nonvolatile
memory programmer, or on-chip boot program
running on the AVR core.
• Boot program can use any interface to
download the application program in the
application flash memory
• Software in the boot flash section continues to
run while the application flash section is
updated, providing true read-while-write
operation.
The device is manufactured using Atmel’s high-
density, nonvolatile memory technology.